Lines Matching refs:cp_eax

372 #define	CPI_FAMILY_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
373 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
374 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
375 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
376 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
377 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
399 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
400 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
401 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
402 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
403 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
404 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
457 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
526 cp->cp_eax &= 0x03fffffff; in platform_cpuid_mangle()
639 cp.cp_eax = 0x1; in determine_platform()
642 cp.cp_eax = 0x40000000; in determine_platform()
688 cp.cp_eax = base; in determine_platform()
695 cp.cp_eax >= (base + 2)) { in determine_platform()
859 cp->cp_eax = 0x8000001e; in cpuid_amd_getids()
968 cp->cp_eax = 0; in cpuid_pass1()
990 cp->cp_eax = 1; in cpuid_pass1()
1073 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; in cpuid_pass1()
1239 ecp->cp_eax = 7; in cpuid_pass1()
1472 cp->cp_eax = 0x80000000; in cpuid_pass1()
1487 cp->cp_eax = 0x80000001; in cpuid_pass1()
1589 cp->cp_eax = 4; in cpuid_pass1()
1599 cp->cp_eax = 0x80000008; in cpuid_pass1()
1607 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); in cpuid_pass1()
1608 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); in cpuid_pass1()
1624 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; in cpuid_pass1()
1656 cp->cp_eax = 0x80000007; in cpuid_pass1()
1760 cp->cp_eax = n; in cpuid_pass2()
1794 BITX(cp->cp_eax, 7, 0); in cpuid_pass2()
1808 if (BITX(cp->cp_eax, 31, 31) == 0) { in cpuid_pass2()
1809 uint8_t *p = (void *)&cp->cp_eax; in cpuid_pass2()
1883 cp->cp_eax = 0xB; in cpuid_pass2()
1903 cp->cp_eax = 0xB; in cpuid_pass2()
1911 coreid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_pass2()
1915 chipid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_pass2()
1942 cp->cp_eax = 0xD; in cpuid_pass2()
1950 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 || in cpuid_pass2()
1951 (cp->cp_eax & XFEATURE_SSE) == 0) { in cpuid_pass2()
1955 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax; in cpuid_pass2()
1964 cp->cp_eax = 0xD; in cpuid_pass2()
1971 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) { in cpuid_pass2()
1975 cpi->cpi_xsave.ymm_size = cp->cp_eax; in cpuid_pass2()
2062 cp->cp_eax = 0x80000000 + n; in cpuid_pass2()
2072 *iptr++ = cp->cp_eax; in cpuid_pass2()
2089 cp->cp_eax = 0; in cpuid_pass2()
2106 cp->cp_eax = cp->cp_ebx = 0; in cpuid_pass2()
2195 tmp = (cp->cp_eax >> (8 * i)) & 0xff; in intel_cpubrand()
2535 cp->cp_eax = 4; in cpuid_pass3()
2571 cp->cp_eax = 4; in cpuid_pass3()
2902 cp.cp_eax = 0x80860001; in cpuid_pass4()
2941 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) in cpuid_insn()
2942 xcp = &cpi->cpi_std[cp->cp_eax]; in cpuid_insn()
2943 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && in cpuid_insn()
2944 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) in cpuid_insn()
2945 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; in cpuid_insn()
2954 cp->cp_eax = xcp->cp_eax; in cpuid_insn()
2958 return (cp->cp_eax); in cpuid_insn()
3036 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, in cpuid_getidstr()
3040 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, in cpuid_getidstr()
3112 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); in cpuid_getsig()
3305 if ((cp->cp_eax & 0xffff0000) == 0) in cpuid_get_dtlb_nent()
3306 dtlb_nent = cp->cp_eax & 0x0000ffff; in cpuid_get_dtlb_nent()
3308 dtlb_nent = BITX(cp->cp_eax, 27, 16); in cpuid_get_dtlb_nent()
3331 dtlb_nent = BITX(cp->cp_eax, 23, 16); in cpuid_get_dtlb_nent()
3365 eax = cpi->cpi_std[1].cp_eax; in cpuid_opteron_erratum()
3530 regs.cp_eax = 0x80000007; in cpuid_opteron_erratum()
4053 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); in amd_cache_info()
4055 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); in amd_cache_info()
4110 if (BITX(cp->cp_eax, 31, 16) == 0) in amd_cache_info()
4112 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4115 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); in amd_cache_info()
4117 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4124 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4127 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); in amd_cache_info()
4129 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); in amd_cache_info()
4294 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); in cpuid_set_cpu_properties()
4628 regs.cp_eax = 0x80000007; in cpuid_deep_cstates_supported()
4715 regs.cp_eax = 6; in cpuid_arat_supported()
4717 return (regs.cp_eax & CPUID_CSTATE_ARAT); in cpuid_arat_supported()
4749 regs.cp_eax = 0x6; in cpuid_iepb_supported()
4775 regs.cp_eax = 1; in cpuid_deadline_tsc_supported()
4825 cp->cp_eax = 0; in cpuid_get_ext_topo()
4828 cp->cp_eax = 0xB; in cpuid_get_ext_topo()
4844 cp->cp_eax = 0xB; in cpuid_get_ext_topo()
4856 coreid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_get_ext_topo()
4863 chipid_shift = BITX(cp->cp_eax, 4, 0); in cpuid_get_ext_topo()