Lines Matching refs:uh
142 } uh; member
479 #define SET_DMAC_CSR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
480 ((uint32_t *)&pp->uh.ebus.dmac->csr), \
482 #define GET_DMAC_CSR(pp) ddi_get32(pp->uh.ebus.d_handle, \
483 (uint32_t *)&(pp->uh.ebus.dmac->csr))
485 #define SET_DMAC_ACR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
486 ((uint32_t *)&pp->uh.ebus.dmac->acr), \
489 #define GET_DMAC_ACR(pp) ddi_get32(pp->uh.ebus.d_handle, \
490 (uint32_t *)&pp->uh.ebus.dmac->acr)
492 #define SET_DMAC_BCR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
493 ((uint32_t *)&pp->uh.ebus.dmac->bcr), \
496 #define GET_DMAC_BCR(pp) ddi_get32(pp->uh.ebus.d_handle, \
497 ((uint32_t *)&pp->uh.ebus.dmac->bcr))