54 #define	ECPP_MAP_REGS(pp)		(pp)->hw->map_regs(pp)  argument
55 #define	ECPP_UNMAP_REGS(pp)		(pp)->hw->unmap_regs(pp)  argument
56 #define	ECPP_CONFIG_CHIP(pp)		(pp)->hw->config_chip(pp)  argument
57 #define	ECPP_CONFIG_MODE(pp)		(pp)->hw->config_mode(pp)  argument
58 #define	ECPP_MASK_INTR(pp)		(pp)->hw->mask_intr(pp)  argument
59 #define	ECPP_UNMASK_INTR(pp)		(pp)->hw->unmask_intr(pp)  argument
60 #define	ECPP_DMA_START(pp)		(pp)->hw->dma_start(pp)  argument
61 #define	ECPP_DMA_STOP(pp, cnt)		(pp)->hw->dma_stop(pp, cnt)  argument
62 #define	ECPP_DMA_GETCNT(pp)		(pp)->hw->dma_getcnt(pp)  argument
412 #define	DSR_READ(pp)		PP_GETB((pp)->i_handle, &(pp)->i_reg->dsr)  argument
413 #define	DCR_READ(pp)		PP_GETB((pp)->i_handle, &(pp)->i_reg->dcr)  argument
414 #define	ECR_READ(pp)		\  argument
416 #define	DATAR_READ(pp)		PP_GETB((pp)->i_handle, &(pp)->i_reg->ir.datar)  argument
417 #define	DFIFO_READ(pp)		\  argument
419 #define	TFIFO_READ(pp)		\  argument
422 #define	DCR_WRITE(pp, val)	PP_PUTB((pp)->i_handle, &(pp)->i_reg->dcr, val)  argument
423 #define	ECR_WRITE(pp, val)	\  argument
425 #define	DATAR_WRITE(pp, val)	\  argument
427 #define	DFIFO_WRITE(pp, val)	\  argument
429 #define	TFIFO_WRITE(pp, val)	\  argument
479 #define	SET_DMAC_CSR(pp, val)	ddi_put32(pp->uh.ebus.d_handle, \  argument
482 #define	GET_DMAC_CSR(pp)	ddi_get32(pp->uh.ebus.d_handle, \  argument
485 #define	SET_DMAC_ACR(pp, val)	ddi_put32(pp->uh.ebus.d_handle, \  argument
489 #define	GET_DMAC_ACR(pp)	ddi_get32(pp->uh.ebus.d_handle, \  argument
492 #define	SET_DMAC_BCR(pp, val)	ddi_put32(pp->uh.ebus.d_handle, \  argument
496 #define	GET_DMAC_BCR(pp)	ddi_get32(pp->uh.ebus.d_handle, \  argument
504 #define	COMPAT_PIO(pp) (((pp)->io_mode == ECPP_PIO) &&		\  argument
508 #define	COMPAT_DMA(pp) (((pp)->io_mode == ECPP_DMA) &&		\  argument