Lines Matching refs:BIT
97 #define BIT(n) (1U << n) macro
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
137 #define PCI_Y2_PHY2_POWD BIT(27) /* Set PHY 2 to Power Down (YUKON-2) */
138 #define PCI_Y2_PHY1_POWD BIT(26) /* Set PHY 1 to Power Down (YUKON-2) */
139 #define PCI_DIS_BOOT BIT(24) /* Disable BOOT via ROM */
140 #define PCI_EN_IO BIT(23) /* Mapping to I/O space */
141 #define PCI_EN_FPROM BIT(22) /* Enable FLASH mapping to memory */
150 #define PCI_PEX_LEGNAT BIT(15) /* PEX PM legacy/native (YUKON-2) */
151 #define PCI_FORCE_BE BIT(14) /* Assert all BEs on MR */
152 #define PCI_DIS_MRL BIT(13) /* Disable Mem Read Line */
153 #define PCI_DIS_MRM BIT(12) /* Disable Mem Read Multiple */
154 #define PCI_DIS_MWI BIT(11) /* Disable Mem Write & Invalidate */
155 #define PCI_DISC_CLS BIT(10) /* Disc: cacheLsz bound */
156 #define PCI_BURST_DIS BIT(9) /* Burst Disable */
157 #define PCI_DIS_PCI_CLK BIT(8) /* Disable PCI clock driving */
160 #define PCI_CLS_OPT BIT(3) /* Cache Line Size PCI-X (YUKON-2) */
168 #define PCI_PATCH_DIR_3 BIT(11)
169 #define PCI_PATCH_DIR_2 BIT(10)
170 #define PCI_PATCH_DIR_1 BIT(9)
171 #define PCI_PATCH_DIR_0 BIT(8)
173 #define PCI_EXT_PATCH_3 BIT(7)
174 #define PCI_EXT_PATCH_2 BIT(6)
175 #define PCI_EXT_PATCH_1 BIT(5)
176 #define PCI_EXT_PATCH_0 BIT(4)
177 #define PCI_EN_DUMMY_RD BIT(3) /* Enable Dummy Read */
178 #define PCI_REV_DESC BIT(2) /* Reverse Desc. Bytes */
179 #define PCI_USEDATA64 BIT(0) /* Use 64Bit Data bus ext */
182 #define PCI_OS_PCI64B BIT(31) /* Conventional PCI 64 bits Bus */
183 #define PCI_OS_PCIX BIT(30) /* PCI-X Bus */
185 #define PCI_OS_PCI66M BIT(27) /* PCI 66 MHz Bus */
186 #define PCI_OS_PCI_X BIT(26) /* PCI/PCI-X Bus (0 = PEX) */
200 #define PCI_FORCE_ASPM_REQUEST BIT(15) /* Force ASPM Request (A1 only) */
201 #define PCI_ASPM_GPHY_LINK_DOWN BIT(14) /* GPHY Link Down (A1 only) */
202 #define PCI_ASPM_INT_FIFO_EMPTY BIT(13) /* Internal FIFO Empty (A1 only) */
203 #define PCI_ASPM_CLKRUN_REQUEST BIT(12) /* CLKRUN Request (A1 only) */
204 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT(4) /* Frc CLKRQ Enbl (A1b only) */
205 #define PCI_ASPM_CLKREQ_PAD_CTL BIT(3) /* CLKREQ PAD Control (A1 only) */
206 #define PCI_ASPM_A1_MODE_SELECT BIT(2) /* A1 Mode Select (A1 only) */
207 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT(1) /* Enable Gate PEX Unit Clock */
208 #define PCI_CLK_GATE_ROOT_COR_ENA BIT(0) /* Enbl Gate Root Core Clock */
217 #define PEX_DC_EN_NO_SNOOP BIT(11) /* Enable No Snoop */
218 #define PEX_DC_EN_AUX_POW BIT(10) /* Enable AUX Power */
219 #define PEX_DC_EN_PHANTOM BIT(9) /* Enable Phantom Functions */
220 #define PEX_DC_EN_EXT_TAG BIT(8) /* Enable Extended Tag Field */
222 #define PEX_DC_EN_REL_ORD BIT(4) /* Enable Relaxed Ordering */
223 #define PEX_DC_EN_UNS_RQ_RP BIT(3) /* Enable Unsupported Request Report */
224 #define PEX_DC_EN_FAT_ER_RP BIT(2) /* Enable Fatal Error Report */
225 #define PEX_DC_EN_NFA_ER_RP BIT(1) /* Enable Non-Fatal Error Report */
226 #define PEX_DC_EN_COR_ER_RP BIT(0) /* Enable Correctable Error Report */
231 #define PEX_LS_SLOT_CLK_CFG BIT(12) /* Slot Clock Config */
232 #define PEX_LS_LINK_TRAIN BIT(11) /* Link Training */
233 #define PEX_LS_TRAIN_ERROR BIT(10) /* Training Error */
238 #define PEX_UNSUP_REQ BIT(20) /* Unsupported Request Error */
239 #define PEX_MALFOR_TLP BIT(18) /* Malformed TLP */
240 #define PEX_RX_OV BIT(17) /* Receiver Overflow (not supported) */
241 #define PEX_UNEXP_COMP BIT(16) /* Unexpected Completion */
242 #define PEX_COMP_TO BIT(14) /* Completion Timeout */
243 #define PEX_FLOW_CTRL_P BIT(13) /* Flow Control Protocol Error */
244 #define PEX_POIS_TLP BIT(12) /* Poisoned TLP */
245 #define PEX_DATA_LINK_P BIT(4) /* Data Link Protocol Error */
611 #define Y2_VMAIN_AVAIL BIT(17) /* VMAIN available (YUKON-2 only) */
612 #define Y2_VAUX_AVAIL BIT(16) /* VAUX available (YUKON-2 only) */
613 #define Y2_HW_WOL_ON BIT(15) /* HW WOL On (Yukon-EC Ultra A1 only) */
614 #define Y2_HW_WOL_OFF BIT(14) /* HW WOL Off (Yukon-EC Ultra A1 only) */
615 #define Y2_ASF_ENABLE BIT(13) /* ASF Unit Enable (YUKON-2 only) */
616 #define Y2_ASF_DISABLE BIT(12) /* ASF Unit Disable (YUKON-2 only) */
617 #define Y2_CLK_RUN_ENA BIT(11) /* CLK_RUN Enable (YUKON-2 only) */
618 #define Y2_CLK_RUN_DIS BIT(10) /* CLK_RUN Disable (YUKON-2 only) */
619 #define Y2_LED_STAT_ON BIT(9) /* Status LED On (YUKON-2 only) */
620 #define Y2_LED_STAT_OFF BIT(8) /* Status LED Off (YUKON-2 only) */
621 #define CS_ST_SW_IRQ BIT(7) /* Set IRQ SW Request */
622 #define CS_CL_SW_IRQ BIT(6) /* Clear IRQ SW Request */
623 #define CS_STOP_DONE BIT(5) /* Stop Master is finished */
624 #define CS_STOP_MAST BIT(4) /* Command Bit to stop the master */
625 #define CS_MRST_CLR BIT(3) /* Clear Master Reset */
626 #define CS_MRST_SET BIT(2) /* Set Master Reset */
627 #define CS_RST_CLR BIT(1) /* Clear Software Reset */
628 #define CS_RST_SET BIT(0) /* Set Software Reset */
630 #define LED_STAT_ON BIT(1) /* Status LED On */
631 #define LED_STAT_OFF BIT(0) /* Status LED Off */
634 #define PC_VAUX_ENA BIT(7) /* Switch VAUX Enable */
635 #define PC_VAUX_DIS BIT(6) /* Switch VAUX Disable */
636 #define PC_VCC_ENA BIT(5) /* Switch VCC Enable */
637 #define PC_VCC_DIS BIT(4) /* Switch VCC Disable */
638 #define PC_VAUX_ON BIT(3) /* Switch VAUX On */
639 #define PC_VAUX_OFF BIT(2) /* Switch VAUX Off */
640 #define PC_VCC_ON BIT(1) /* Switch VCC On */
641 #define PC_VCC_OFF BIT(0) /* Switch VCC Off */
652 #define Y2_IS_HW_ERR BIT(31) /* Interrupt HW Error */
653 #define Y2_IS_STAT_BMU BIT(30) /* Status BMU Interrupt */
654 #define Y2_IS_ASF BIT(29) /* ASF subsystem Interrupt */
655 #define Y2_IS_POLL_CHK BIT(27) /* Check IRQ from polling unit */
656 #define Y2_IS_TWSI_RDY BIT(26) /* IRQ on end of TWSI Tx */
657 #define Y2_IS_IRQ_SW BIT(25) /* SW forced IRQ */
658 #define Y2_IS_TIMINT BIT(24) /* IRQ from Timer */
659 #define Y2_IS_IRQ_PHY2 BIT(12) /* Interrupt from PHY 2 */
660 #define Y2_IS_IRQ_MAC2 BIT(11) /* Interrupt from MAC 2 */
661 #define Y2_IS_CHK_RX2 BIT(10) /* Descriptor error Rx 2 */
662 #define Y2_IS_CHK_TXS2 BIT(9) /* Descriptor error TXS 2 */
663 #define Y2_IS_CHK_TXA2 BIT(8) /* Descriptor error TXA 2 */
664 #define Y2_IS_IRQ_PHY1 BIT(4) /* Interrupt from PHY 1 */
665 #define Y2_IS_IRQ_MAC1 BIT(3) /* Interrupt from MAC 1 */
666 #define Y2_IS_CHK_RX1 BIT(2) /* Descriptor error Rx 1 */
667 #define Y2_IS_CHK_TXS1 BIT(1) /* Descriptor error TXS 1 */
668 #define Y2_IS_CHK_TXA1 BIT(0) /* Descriptor error TXA 1 */
682 #define Y2_IS_TIST_OV BIT(29) /* Time Stamp Timer overflow interrupt */
683 #define Y2_IS_SENSOR BIT(28) /* Sensor interrupt */
684 #define Y2_IS_MST_ERR BIT(27) /* Master error interrupt */
685 #define Y2_IS_IRQ_STAT BIT(26) /* Status exception interrupt */
686 #define Y2_IS_PCI_EXP BIT(25) /* PCI-Express interrupt */
687 #define Y2_IS_PCI_NEXP BIT(24) /* PCI-Express error similar to PCI error */
688 #define Y2_IS_PAR_RD2 BIT(13) /* Read RAM parity error interrupt */
689 #define Y2_IS_PAR_WR2 BIT(12) /* Write RAM parity error interrupt */
690 #define Y2_IS_PAR_MAC2 BIT(11) /* MAC hardware fault interrupt */
691 #define Y2_IS_PAR_RX2 BIT(10) /* Parity Error Rx Queue 2 */
692 #define Y2_IS_TCP_TXS2 BIT(9) /* TCP length mismatch sync Tx queue IRQ */
693 #define Y2_IS_TCP_TXA2 BIT(8) /* TCP length mismatch async Tx queue IRQ */
694 #define Y2_IS_PAR_RD1 BIT(5) /* Read RAM parity error interrupt */
695 #define Y2_IS_PAR_WR1 BIT(4) /* Write RAM parity error interrupt */
696 #define Y2_IS_PAR_MAC1 BIT(3) /* MAC hardware fault interrupt */
697 #define Y2_IS_PAR_RX1 BIT(2) /* Parity Error Rx Queue 1 */
698 #define Y2_IS_TCP_TXS1 BIT(1) /* TCP length mismatch sync Tx queue IRQ */
699 #define Y2_IS_TCP_TXA1 BIT(0) /* TCP length mismatch async Tx queue IRQ */
712 #define CFG_DIS_M2_CLK BIT(1) /* Disable Clock for 2nd MAC */
713 #define CFG_SNG_MAC BIT(0) /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
763 #define Y2_STATUS_LNK2_INAC BIT(7) /* Status Link 2 inactiv (0 = activ) */
764 #define Y2_CLK_GAT_LNK2_DIS BIT(6) /* Disable clock gating Link 2 */
765 #define Y2_COR_CLK_LNK2_DIS BIT(5) /* Disable Core clock Link 2 */
766 #define Y2_PCI_CLK_LNK2_DIS BIT(4) /* Disable PCI clock Link 2 */
767 #define Y2_STATUS_LNK1_INAC BIT(3) /* Status Link 1 inactiv (0 = activ) */
768 #define Y2_CLK_GAT_LNK1_DIS BIT(2) /* Disable clock gating Link 1 */
769 #define Y2_COR_CLK_LNK1_DIS BIT(1) /* Disable Core clock Link 1 */
770 #define Y2_PCI_CLK_LNK1_DIS BIT(0) /* Disable PCI clock Link 1 */
774 #define CFG_LINK_2_AVAIL BIT(1) /* Link 2 available */
775 #define CFG_LINK_1_AVAIL BIT(0) /* Link 1 available */
792 #define Y2_CLK_DIV_ENA BIT(1) /* Enable Core Clock Division */
793 #define Y2_CLK_DIV_DIS BIT(0) /* Disable Core Clock Division */
797 #define TIM_START BIT(2) /* Start Timer */
798 #define TIM_STOP BIT(1) /* Stop Timer */
799 #define TIM_CLR_IRQ BIT(0) /* Clear Timer IRQ (!IRQM) */
804 #define TIM_T_ON BIT(2) /* Test mode on */
805 #define TIM_T_OFF BIT(1) /* Test mode off */
806 #define TIM_T_STEP BIT(0) /* Test step */
813 #define DPT_START BIT(1) /* Start Descriptor Poll Timer */
814 #define DPT_STOP BIT(0) /* Stop Descriptor Poll Timer */
817 #define TST_FRC_DPERR_MR BIT(7) /* force DATAPERR on MST RD */
818 #define TST_FRC_DPERR_MW BIT(6) /* force DATAPERR on MST WR */
819 #define TST_FRC_DPERR_TR BIT(5) /* force DATAPERR on TRG RD */
820 #define TST_FRC_DPERR_TW BIT(4) /* force DATAPERR on TRG WR */
821 #define TST_FRC_APERR_M BIT(3) /* force ADDRPERR on MST */
822 #define TST_FRC_APERR_T BIT(2) /* force ADDRPERR on TRG */
823 #define TST_CFG_WRITE_ON BIT(1) /* Enable Config Reg WR */
824 #define TST_CFG_WRITE_OFF BIT(0) /* Disable Config Reg WR */
827 #define I2C_FLAG BIT(31) /* Start read/write if WR */
830 #define I2C_BURST_LEN BIT(4) /* Burst Len, 1/4 bytes */
840 #define I2C_STOP BIT(0) /* Interrupt I2C transfer */
843 #define I2C_CLR_IRQ BIT(0) /* Clear I2C IRQ */
846 #define I2C_DATA_DIR BIT(2) /* direction of I2C_DATA */
847 #define I2C_DATA BIT(1) /* I2C Data Port */
848 #define I2C_CLK BIT(0) /* I2C Clock Port */
855 #define BSC_START BIT(1) /* Start Blink Source Counter */
856 #define BSC_STOP BIT(0) /* Stop Blink Source Counter */
859 #define BSC_SRC BIT(0) /* Blink Source, 0=Off / 1=On */
862 #define BSC_T_ON BIT(2) /* Test mode on */
863 #define BSC_T_OFF BIT(1) /* Test mode off */
864 #define BSC_T_STEP BIT(0) /* Test step */
867 #define GLB_GPIO_CLK_DEB_ENA BIT(31) /* Clock Debug Enable */
873 #define GLB_GPIO_INT_RST_D3_DIS BIT(15)
874 #define GLB_GPIO_LED_PAD_SPEED_UP BIT(14) /* LED PAD Speed Up */
875 #define GLB_GPIO_STAT_RACE_DIS BIT(13) /* Status Race Disable */
878 #define GLB_GPIO_RAND_ENA BIT(10) /* Random Enable */
879 #define GLB_GPIO_RAND_BIT_1 BIT(9) /* Random Bit 1 */
884 #define PEX_RD_ACCESS BIT(31) /* Access Mode Read = 1, Write = 0 */
885 #define PEX_DB_ACCESS BIT(30) /* Access to debug register */
892 #define RI_CLR_RD_PERR BIT(9) /* Clear IRQ RAM Read Parity Err */
893 #define RI_CLR_WR_PERR BIT(8) /* Clear IRQ RAM Write Parity Err */
894 #define RI_RST_CLR BIT(1) /* Clear RAM Interface Reset */
895 #define RI_RST_SET BIT(0) /* Set RAM Interface Reset */
907 #define TXA_ENA_FSYNC BIT(7) /* Enable force of sync Tx queue */
908 #define TXA_DIS_FSYNC BIT(6) /* Disable force of sync Tx queue */
909 #define TXA_ENA_ALLOC BIT(5) /* Enable alloc of free bandwidth */
910 #define TXA_DIS_ALLOC BIT(4) /* Disable alloc of free bandwidth */
911 #define TXA_START_RC BIT(3) /* Start sync Rate Control */
912 #define TXA_STOP_RC BIT(2) /* Stop sync Rate Control */
913 #define TXA_ENA_ARB BIT(1) /* Enable Tx Arbiter */
914 #define TXA_DIS_ARB BIT(0) /* Disable Tx Arbiter */
917 #define TXA_INT_T_ON BIT(5) /* Tx Arb Interval Timer Test On */
918 #define TXA_INT_T_OFF BIT(4) /* Tx Arb Interval Timer Test Off */
919 #define TXA_INT_T_STEP BIT(3) /* Tx Arb Interval Timer Step */
920 #define TXA_LIM_T_ON BIT(2) /* Tx Arb Limit Timer Test On */
921 #define TXA_LIM_T_OFF BIT(1) /* Tx Arb Limit Timer Test Off */
922 #define TXA_LIM_T_STEP BIT(0) /* Tx Arb Limit Timer Step */
925 #define TXA_PRIO_XS BIT(0) /* sync queue has prio to send */
931 #define BMU_IDLE BIT(31) /* BMU Idle State */
932 #define BMU_RX_TCP_PKT BIT(30) /* Rx TCP Packet (when RSS Hash enab) */
933 #define BMU_RX_IP_PKT BIT(29) /* Rx IP Packet (when RSS Hash enab) */
934 #define BMU_ENA_RX_RSS_HASH BIT(15) /* Enable Rx RSS Hash */
935 #define BMU_DIS_RX_RSS_HASH BIT(14) /* Disable Rx RSS Hash */
936 #define BMU_ENA_RX_CHKSUM BIT(13) /* Enable Rx TCP/IP Checksum Check */
937 #define BMU_DIS_RX_CHKSUM BIT(12) /* Disable Rx TCP/IP Checksum Check */
938 #define BMU_CLR_IRQ_PAR BIT(11) /* Clear IRQ on Parity errors (Rx) */
939 #define BMU_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP seg. error (Tx) */
940 #define BMU_CLR_IRQ_CHK BIT(10) /* Clear IRQ Check */
941 #define BMU_STOP BIT(9) /* Stop Rx/Tx Queue */
942 #define BMU_START BIT(8) /* Start Rx/Tx Queue */
943 #define BMU_FIFO_OP_ON BIT(7) /* FIFO Operational On */
944 #define BMU_FIFO_OP_OFF BIT(6) /* FIFO Operational Off */
945 #define BMU_FIFO_ENA BIT(5) /* Enable FIFO */
946 #define BMU_FIFO_RST BIT(4) /* Reset FIFO */
947 #define BMU_OP_ON BIT(3) /* BMU Operational On */
948 #define BMU_OP_OFF BIT(2) /* BMU Operational Off */
949 #define BMU_RST_CLR BIT(1) /* Clear BMU Reset (Enable) */
950 #define BMU_RST_SET BIT(0) /* Set BMU Reset */
958 #define BMU_TX_IPIDINCR_ON BIT(13) /* Enable IP ID Increment */
959 #define BMU_TX_IPIDINCR_OFF BIT(12) /* Disable IP ID Increment */
960 #define BMU_TX_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP segm. len mism. */
964 #define F_TX_CHK_AUTO_OFF BIT(31) /* Tx csum auto-calc Off (Yukon EX) */
965 #define F_TX_CHK_AUTO_ON BIT(30) /* Tx csum auto-calc On (Yukon EX) */
966 #define F_ALM_FULL BIT(27) /* Rx FIFO: almost full */
967 #define F_EMPTY BIT(27) /* Tx FIFO: empty flag */
968 #define F_FIFO_EOF BIT(26) /* Tag (EOF Flag) bit in FIFO */
969 #define F_WM_REACHED BIT(25) /* Watermark reached */
970 #define F_M_RX_RAM_DIS BIT(24) /* MAC Rx RAM Read Port disable */
976 #define PREF_UNIT_OP_ON BIT(3) /* prefetch unit operational */
977 #define PREF_UNIT_OP_OFF BIT(2) /* prefetch unit not operational */
978 #define PREF_UNIT_RST_CLR BIT(1) /* Clear Prefetch Unit Reset */
979 #define PREF_UNIT_RST_SET BIT(0) /* Set Prefetch Unit Reset */
995 #define RB_PC_DEC BIT(3) /* Packet Counter Decrement */
996 #define RB_PC_T_ON BIT(2) /* Packet Counter Test On */
997 #define RB_PC_T_OFF BIT(1) /* Packet Counter Test Off */
998 #define RB_PC_INC BIT(0) /* Packet Counter Increment */
1001 #define RB_WP_T_ON BIT(6) /* Write Pointer Test On */
1002 #define RB_WP_T_OFF BIT(5) /* Write Pointer Test Off */
1003 #define RB_WP_INC BIT(4) /* Write Pointer Increment */
1004 #define RB_RP_T_ON BIT(2) /* Read Pointer Test On */
1005 #define RB_RP_T_OFF BIT(1) /* Read Pointer Test Off */
1006 #define RB_RP_INC BIT(0) /* Read Pointer Increment */
1009 #define RB_ENA_STFWD BIT(5) /* Enable Store & Forward */
1010 #define RB_DIS_STFWD BIT(4) /* Disable Store & Forward */
1011 #define RB_ENA_OP_MD BIT(3) /* Enable Operation Mode */
1012 #define RB_DIS_OP_MD BIT(2) /* Disable Operation Mode */
1013 #define RB_RST_CLR BIT(1) /* Clear RAM Buf STM Reset */
1014 #define RB_RST_SET BIT(0) /* Set RAM Buf STM Reset */
1059 #define WOL_CTL_LINK_CHG_OCC BIT(15)
1060 #define WOL_CTL_MAGIC_PKT_OCC BIT(14)
1061 #define WOL_CTL_PATTERN_OCC BIT(13)
1062 #define WOL_CTL_CLEAR_RESULT BIT(12)
1063 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT(11)
1064 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT(10)
1065 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT(9)
1066 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT(8)
1067 #define WOL_CTL_ENA_PME_ON_PATTERN BIT(7)
1068 #define WOL_CTL_DIS_PME_ON_PATTERN BIT(6)
1069 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT(5)
1070 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT(4)
1071 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT(3)
1072 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT(2)
1073 #define WOL_CTL_ENA_PATTERN_UNIT BIT(1)
1074 #define WOL_CTL_DIS_PATTERN_UNIT BIT(0)
1085 #define WOL_CTL_PATT_ENA(x) (BIT(0) << (x))
1088 #define WOL_PATT_FORCE_PME BIT(7) /* Generates a PME */
1133 #define PHY_M_PC_ASS_CRS_TX BIT(11) /* Assert CRS on Transmit */
1134 #define PHY_M_PC_FL_GOOD BIT(10) /* Force Link Good */
1136 #define PHY_M_PC_ENA_EXT_D BIT(7) /* Enable Ext. Distance (10BT) */
1138 #define PHY_M_PC_DIS_125CLK BIT(4) /* Disable 125 CLK */
1139 #define PHY_M_PC_MAC_POW_UP BIT(3) /* MAC Power up */
1140 #define PHY_M_PC_SQE_T_ENA BIT(2) /* SQE Test Enabled */
1141 #define PHY_M_PC_POL_R_DIS BIT(1) /* Polarity Reversal Disabled */
1142 #define PHY_M_PC_DIS_JABBER BIT(0) /* Disable Jabber */
1154 #define PHY_M_PC_DIS_LINK_P BIT(15) /* Disable Link Pulses */
1156 #define PHY_M_PC_DOWN_S_ENA BIT(11) /* Downshift Enable */
1158 #define PHY_M_PC_COP_TX_DIS BIT(3)
1159 #define PHY_M_PC_POW_D_ENA BIT(2)
1166 #define PHY_M_PC_ENA_DTE_DT BIT(15) /* Enable (DTE) Detect */
1167 #define PHY_M_PC_ENA_ENE_DT BIT(14) /* Enable Energy Det (sense & pulse) */
1168 #define PHY_M_PC_DIS_NLP_CK BIT(13) /* Dis. Normal Link Puls (NLP) Check */
1169 #define PHY_M_PC_ENA_LIP_NP BIT(12) /* Enable Link Partner Next Page Reg. */
1170 #define PHY_M_PC_DIS_NLP_GN BIT(11) /* Dis. Normal Link Puls Generation */
1171 #define PHY_M_PC_DIS_SCRAMB BIT(9) /* Dis. Scrambler */
1172 #define PHY_M_PC_DIS_FEFI BIT(8) /* Dis. Far End Fault Indic. (FEFI) */
1173 #define PHY_M_PC_SH_TP_SEL BIT(6) /* Shielded Twisted Pair Select */
1178 #define PHY_M_PS_SPEED_1000 BIT(15) /* 10 = 1000 Mbps */
1179 #define PHY_M_PS_SPEED_100 BIT(14) /* 01 = 100 Mbps */
1181 #define PHY_M_PS_FULL_DUP BIT(13) /* Full Duplex */
1182 #define PHY_M_PS_PAGE_REC BIT(12) /* Page Received */
1183 #define PHY_M_PS_SPDUP_RES BIT(11) /* Speed & Duplex Resolved */
1184 #define PHY_M_PS_LINK_UP BIT(10) /* Link Up */
1186 #define PHY_M_PS_MDI_X_STAT BIT(6) /* MDI Crossover Stat (1=MDIX) */
1187 #define PHY_M_PS_DOWNS_STAT BIT(5) /* Downshift Status (1=downsh.) */
1188 #define PHY_M_PS_ENDET_STAT BIT(4) /* Energy Detect Status (1=act) */
1189 #define PHY_M_PS_TX_P_EN BIT(3) /* Tx Pause Enabled */
1190 #define PHY_M_PS_RX_P_EN BIT(2) /* Rx Pause Enabled */
1191 #define PHY_M_PS_POL_REV BIT(1) /* Polarity Reversed */
1192 #define PHY_M_PS_JABBER BIT(0) /* Jabber */
1197 #define PHY_M_PS_DTE_DETECT BIT(15) /* DTE Detected */
1198 #define PHY_M_PS_RES_SPEED BIT(14) /* Resolved Speed (1=100, 0=10) */
1202 #define PHY_M_IS_AN_ERROR BIT(15) /* Auto-Negotiation Error */
1203 #define PHY_M_IS_LSP_CHANGE BIT(14) /* Link Speed Changed */
1204 #define PHY_M_IS_DUP_CHANGE BIT(13) /* Duplex Mode Changed */
1205 #define PHY_M_IS_AN_PR BIT(12) /* Page Received */
1206 #define PHY_M_IS_AN_COMPL BIT(11) /* Auto-Negotiation Completed */
1207 #define PHY_M_IS_LST_CHANGE BIT(10) /* Link Status Changed */
1208 #define PHY_M_IS_SYMB_ERROR BIT(9) /* Symbol Error */
1209 #define PHY_M_IS_FALSE_CARR BIT(8) /* False Carrier */
1210 #define PHY_M_IS_FIFO_ERROR BIT(7) /* FIFO Overflow/Underrun Error */
1211 #define PHY_M_IS_MDI_CHANGE BIT(6) /* MDI Crossover Changed */
1212 #define PHY_M_IS_DOWNSH_DET BIT(5) /* Downshift Detected */
1213 #define PHY_M_IS_END_CHANGE BIT(4) /* Energy Detect Changed */
1214 #define PHY_M_IS_DTE_CHANGE BIT(2) /* DTE Power Det. Status Changed */
1215 #define PHY_M_IS_POL_CHANGE BIT(1) /* Polarity Changed */
1216 #define PHY_M_IS_JABBER BIT(0) /* Jabber */
1224 #define PHY_M_EC_ENA_BC_EXT BIT(15) /* Enbl Blck Car. Ext. (88E1111 only) */
1225 #define PHY_M_EC_ENA_LIN_LB BIT(14) /* Enbl Line Loopback (88E1111 only) */
1226 #define PHY_M_EC_DIS_LINK_P BIT(12) /* Disable Link Pulses (88E1111 only) */
1233 #define PHY_M_EC_DOWN_S_ENA BIT(8) /* Downshift Enable (88E1111 only) */
1235 #define PHY_M_EC_RX_TIM_CT BIT(7) /* RGMII Rx Timing Control */
1237 #define PHY_M_EC_FIB_AN_ENA BIT(3) /* Fbr Aut-Neg. Enbl (88E1011S only) */
1238 #define PHY_M_EC_DTE_D_ENA BIT(2) /* DTE Detect Enable (88E1111 only) */
1239 #define PHY_M_EC_TX_TIM_CT BIT(1) /* RGMII Tx Timing Control */
1240 #define PHY_M_EC_TRANS_DIS BIT(0) /* Transttr Disable (88E1111 only) */
1257 #define PHY_M_LEDC_DIS_LED BIT(15) /* Disable LED */
1259 #define PHY_M_LEDC_F_INT BIT(11) /* Force Interrupt */
1261 #define PHY_M_LEDC_DP_C_LSB BIT(7) /* Duplex Control (LSB, 88E1111 only) */
1262 #define PHY_M_LEDC_TX_C_LSB BIT(6) /* Tx Control (LSB, 88E1111 only) */
1267 #define PHY_M_LEDC_DP_CTRL BIT(2) /* Duplex Control */
1268 #define PHY_M_LEDC_DP_C_MSB BIT(2) /* Duplex Control (MSB, 88E1111 only) */
1269 #define PHY_M_LEDC_RX_CTRL BIT(1) /* Rx Activity / Link */
1270 #define PHY_M_LEDC_TX_CTRL BIT(0) /* Tx Activity / Link */
1271 #define PHY_M_LEDC_TX_C_MSB BIT(0) /* Tx Control (MSB, 88E1111 only) */
1307 #define PHY_M_EC2_FI_IMPED BIT(6) /* Fiber Input Impedance */
1308 #define PHY_M_EC2_FO_IMPED BIT(5) /* Fiber Output Impedance */
1309 #define PHY_M_EC2_FO_M_CLK BIT(4) /* Fiber Mode Clock Enable */
1310 #define PHY_M_EC2_FO_BOOST BIT(3) /* Fiber Output Boost */
1314 #define PHY_M_FC_AUTO_SEL BIT(15) /* Fiber/Copper Auto Sel. Dis. */
1315 #define PHY_M_FC_AN_REG_ACC BIT(14) /* Fiber/Copper AN Reg. Access */
1316 #define PHY_M_FC_RESOLUTION BIT(13) /* Fiber/Copper Resolution */
1317 #define PHY_M_SER_IF_AN_BP BIT(12) /* Ser. IF AN Bypass Enable */
1318 #define PHY_M_SER_IF_BP_ST BIT(11) /* Ser. IF AN Bypass Status */
1319 #define PHY_M_IRQ_POLARITY BIT(10) /* IRQ polarity */
1320 #define PHY_M_DIS_AUT_MED BIT(9) /* Disable Aut. Medium Reg. Selection */
1322 #define PHY_M_UNDOC1 BIT(7) /* undocumented bit !! */
1323 #define PHY_M_DTE_POW_STAT BIT(4) /* DTE Power Status (88E1111 only) */
1327 #define PHY_M_CABD_ENA_TEST BIT(15) /* Enable Test (Page 0) */
1328 #define PHY_M_CABD_DIS_WAIT BIT(15) /* Disable Waiting Period (Page 1) */
1369 #define PHY_M_FESC_DIS_WAIT BIT(2) /* Disable TDR Waiting Period */
1370 #define PHY_M_FESC_ENA_MCLK BIT(1) /* Enable MAC Rx Clock in sleep mode */
1371 #define PHY_M_FESC_SEL_CL_A BIT(0) /* Select Class A driver (100B-TX) */
1375 #define PHY_M_FIB_FORCE_LNK BIT(10) /* Force Link Good */
1376 #define PHY_M_FIB_SIGD_POL BIT(9) /* SIGDET Polarity */
1377 #define PHY_M_FIB_TX_DIS BIT(3) /* Transmitter Disable */
1381 #define PHY_M_MAC_GMIF_PUP BIT(3)
1525 #define GM_GPSR_SPEED BIT(15) /* Port Speed (1 = 100 Mbps) */
1526 #define GM_GPSR_DUPLEX BIT(14) /* Duplex Mode (1 = Full) */
1527 #define GM_GPSR_FC_TX_DIS BIT(13) /* Tx Flow-Control Mode Disabled */
1528 #define GM_GPSR_LINK_UP BIT(12) /* Link Up Status */
1529 #define GM_GPSR_PAUSE BIT(11) /* Pause State */
1530 #define GM_GPSR_TX_ACTIVE BIT(10) /* Tx in Progress */
1531 #define GM_GPSR_EXC_COL BIT(9) /* Excessive Collisions Occured */
1532 #define GM_GPSR_LAT_COL BIT(8) /* Late Collisions Occured */
1533 #define GM_GPSR_PHY_ST_CH BIT(5) /* PHY Status Change */
1534 #define GM_GPSR_GIG_SPEED BIT(4) /* Gigabit Speed (1 = 1000 Mbps) */
1535 #define GM_GPSR_PART_MODE BIT(3) /* Partition mode */
1536 #define GM_GPSR_FC_RX_DIS BIT(2) /* Rx Flow-Control Mode Disabled */
1539 #define GM_GPCR_RMII_PH_ENA BIT(15) /* Enbl RMII for PHY (Yukon-FE only) */
1540 #define GM_GPCR_RMII_LB_ENA BIT(14) /* Enable RMII Lpbck (Yukon-FE only) */
1541 #define GM_GPCR_FC_TX_DIS BIT(13) /* Disable Tx Flow-Control Mode */
1542 #define GM_GPCR_TX_ENA BIT(12) /* Enable Transmit */
1543 #define GM_GPCR_RX_ENA BIT(11) /* Enable Receive */
1544 #define GM_GPCR_LOOP_ENA BIT(9) /* Enable MAC Loopback Mode */
1545 #define GM_GPCR_PART_ENA BIT(8) /* Enable Partition Mode */
1546 #define GM_GPCR_GIGS_ENA BIT(7) /* Gigabit Speed (1000 Mbps) */
1547 #define GM_GPCR_FL_PASS BIT(6) /* Force Link Pass */
1548 #define GM_GPCR_DUP_FULL BIT(5) /* Full Duplex Mode */
1549 #define GM_GPCR_FC_RX_DIS BIT(4) /* Disable Rx Flow-Control Mode */
1550 #define GM_GPCR_SPEED_100 BIT(3) /* Port Speed 100 Mbps */
1551 #define GM_GPCR_AU_DUP_DIS BIT(2) /* Disable Auto-Update Duplex */
1552 #define GM_GPCR_AU_FCT_DIS BIT(1) /* Disable Auto-Update Flow-C. */
1553 #define GM_GPCR_AU_SPD_DIS BIT(0) /* Disable Auto-Update Speed */
1560 #define GM_TXCR_FORCE_JAM BIT(15) /* Force Jam / Flow-Control */
1561 #define GM_TXCR_CRC_DIS BIT(14) /* Disable insertion of CRC */
1562 #define GM_TXCR_PAD_DIS BIT(13) /* Disable padding of packets */
1571 #define GM_RXCR_UCF_ENA BIT(15) /* Enable Unicast filtering */
1572 #define GM_RXCR_MCF_ENA BIT(14) /* Enable Multicast filtering */
1573 #define GM_RXCR_CRC_DIS BIT(13) /* Remove 4-byte CRC */
1574 #define GM_RXCR_PASS_FC BIT(12) /* Pass FC pckts FIFO (Yukon-1 only) */
1596 #define GM_SMOD_LIMIT_4 BIT(10) /* 4 consecutive Tx trials */
1597 #define GM_SMOD_VLAN_ENA BIT(9) /* Enable VLAN (Max. Frame Len) */
1598 #define GM_SMOD_JUMBO_ENA BIT(8) /* Enable Jumbo (Max. Frame Len) */
1599 #define GM_NEW_FLOW_CTRL BIT(6) /* Enable New Flow-Control */
1611 #define GM_SMI_CT_OP_RD BIT(5) /* OpCode Read (0=Write) */
1612 #define GM_SMI_CT_RD_VAL BIT(4) /* Read Valid (Read completed) */
1613 #define GM_SMI_CT_BUSY BIT(3) /* Busy (Operation in progress) */
1619 #define GM_PAR_MIB_CLR BIT(5) /* Set MIB Clear Counter Mode */
1620 #define GM_PAR_MIB_TST BIT(4) /* MIB Load Counter (Test Mode) */
1624 #define GMR_FS_VLAN BIT(13) /* VLAN Packet */
1625 #define GMR_FS_JABBER BIT(12) /* Jabber Packet */
1626 #define GMR_FS_UN_SIZE BIT(11) /* Undersize Packet */
1627 #define GMR_FS_MC BIT(10) /* Multicast Packet */
1628 #define GMR_FS_BC BIT(9) /* Broadcast Packet */
1629 #define GMR_FS_RX_OK BIT(8) /* Receive OK (Good Packet) */
1630 #define GMR_FS_GOOD_FC BIT(7) /* Good Flow-Control Packet */
1631 #define GMR_FS_BAD_FC BIT(6) /* Bad Flow-Control Packet */
1632 #define GMR_FS_MII_ERR BIT(5) /* MII Error */
1633 #define GMR_FS_LONG_ERR BIT(4) /* Too Long Packet */
1634 #define GMR_FS_FRAGMENT BIT(3) /* Fragment */
1635 #define GMR_FS_CRC_ERR BIT(1) /* CRC Error */
1636 #define GMR_FS_RX_FF_OV BIT(0) /* Rx FIFO Overflow */
1672 #define RX_TRUNC_ON BIT(27) /* enable packet truncation */
1673 #define RX_TRUNC_OFF BIT(26) /* disable packet truncation */
1674 #define RX_VLAN_STRIP_ON BIT(25) /* enable VLAN stripping */
1675 #define RX_VLAN_STRIP_OFF BIT(24) /* disable VLAN stripping */
1676 #define GMF_RX_OVER_ON BIT(19) /* flushing on receive overrun */
1677 #define GMF_RX_OVER_OFF BIT(18) /* flushing on receive overrun */
1678 #define GMF_WP_TST_ON BIT(14) /* Write Pointer Test On */
1679 #define GMF_WP_TST_OFF BIT(13) /* Write Pointer Test Off */
1680 #define GMF_WP_STEP BIT(12) /* Write Pointer Step/Increment */
1681 #define GMF_RP_TST_ON BIT(10) /* Read Pointer Test On */
1682 #define GMF_RP_TST_OFF BIT(9) /* Read Pointer Test Off */
1683 #define GMF_RP_STEP BIT(8) /* Read Pointer Step/Increment */
1684 #define GMF_RX_F_FL_ON BIT(7) /* Rx FIFO Flush Mode On */
1685 #define GMF_RX_F_FL_OFF BIT(6) /* Rx FIFO Flush Mode Off */
1686 #define GMF_CLI_RX_FO BIT(5) /* Clear IRQ Rx FIFO Overrun */
1687 #define GMF_CLI_RX_FC BIT(4) /* Clear IRQ Rx Frame Complete */
1688 #define GMF_OPER_ON BIT(3) /* Operational Mode On */
1689 #define GMF_OPER_OFF BIT(2) /* Operational Mode Off */
1690 #define GMF_RST_CLR BIT(1) /* Clear GMAC FIFO Reset */
1691 #define GMF_RST_SET BIT(0) /* Set GMAC FIFO Reset */
1694 #define TX_STFW_DIS BIT(31) /* Disable Store & Forward (Yukon-EC Ultra) */
1695 #define TX_STFW_ENA BIT(30) /* Enable Store & Forward (Yukon-EC Ultra) */
1696 #define TX_VLAN_TAG_ON BIT(25) /* enable VLAN tagging */
1697 #define TX_VLAN_TAG_OFF BIT(24) /* disable VLAN tagging */
1698 #define TX_JUMBO_ENA BIT(23) /* Enable Jumbo Mode (Yukon-EC Ultra) */
1699 #define TX_JUMBO_DIS BIT(22) /* Disable Jumbo Mode (Yukon-EC Ultra) */
1700 #define GMF_WSP_TST_ON BIT(18) /* Write Shadow Pointer Test On */
1701 #define GMF_WSP_TST_OFF BIT(17) /* Write Shadow Pointer Test Off */
1702 #define GMF_WSP_STEP BIT(16) /* Write Shadow Pointer Step/Increment */
1704 #define GMF_CLI_TX_FU BIT(6) /* Clear IRQ Tx FIFO Underrun */
1705 #define GMF_CLI_TX_FC BIT(5) /* Clear IRQ Tx Frame Complete */
1706 #define GMF_CLI_TX_PE BIT(4) /* Clear IRQ Tx Parity Error */
1716 #define GMT_ST_START BIT(2) /* Start Time Stamp Timer */
1717 #define GMT_ST_STOP BIT(1) /* Stop Time Stamp Timer */
1718 #define GMT_ST_CLR_IRQ BIT(0) /* Clear Time Stamp Timer IRQ */
1721 #define PC_CLR_IRQ_CHK BIT(5) /* Clear IRQ Check */
1722 #define PC_POLL_RQ BIT(4) /* Poll Request Start */
1723 #define PC_POLL_OP_ON BIT(3) /* Operational Mode On */
1724 #define PC_POLL_OP_OFF BIT(2) /* Operational Mode Off */
1725 #define PC_POLL_RST_CLR BIT(1) /* Clear Polling Unit Reset (Enable) */
1726 #define PC_POLL_RST_SET BIT(0) /* Set Polling Unit Reset */
1730 #define Y2_ASF_AHB_RST BIT(9) /* AHB bridge reset */
1731 #define Y2_ASF_CPU_MODE BIT(8) /* ASF CPU reset mode */
1732 #define Y2_ASF_OS_PRES BIT(4) /* ASF operation system present */
1733 #define Y2_ASF_RESET BIT(3) /* ASF system in reset state */
1734 #define Y2_ASF_RUNNING BIT(2) /* ASF system operational */
1735 #define Y2_ASF_CLR_HSTI BIT(1) /* Clear ASF IRQ */
1736 #define Y2_ASF_IRQ BIT(0) /* Issue an IRQ to ASF system */
1744 #define Y2_ASF_CLR_ASFI BIT(1) /* Clear host IRQ */
1745 #define Y2_ASF_HOST_IRQ BIT(0) /* Issue an IRQ to HOST system */
1748 #define SC_STAT_CLR_IRQ BIT(4) /* Status Burst IRQ clear */
1749 #define SC_STAT_OP_ON BIT(3) /* Operational Mode On */
1750 #define SC_STAT_OP_OFF BIT(2) /* Operational Mode Off */
1751 #define SC_STAT_RST_CLR BIT(1) /* Clear Status Unit Reset (Enable) */
1752 #define SC_STAT_RST_SET BIT(0) /* Set Status Unit Reset */
1755 #define GMC_SET_RST BIT(15) /* MAC SEC RST */
1756 #define GMC_SEC_RST_OFF BIT(14) /* MAC SEC RST OFF */
1757 #define GMC_BYP_MACSECRX_ON BIT(13) /* Bypass macsec RX */
1758 #define GMC_BYP_MACSECRX_OFF BIT(12) /* Bypass macsec RX off */
1759 #define GMC_BYP_MACSECTX_ON BIT(11) /* Bypass macsec TX */
1760 #define GMC_BYP_MACSECTX_OFF BIT(10) /* Bypass macsec TX off */
1761 #define GMC_BYP_RETR_ON BIT(9) /* Bypass retransmit FIFO On */
1762 #define GMC_BYP_RETR_OFF BIT(8) /* Bypass retransmit FIFO Off */
1763 #define GMC_H_BURST_ON BIT(7) /* Half Duplex Burst Mode On */
1764 #define GMC_H_BURST_OFF BIT(6) /* Half Duplex Burst Mode Off */
1765 #define GMC_F_LOOPB_ON BIT(5) /* FIFO Loopback On */
1766 #define GMC_F_LOOPB_OFF BIT(4) /* FIFO Loopback Off */
1767 #define GMC_PAUSE_ON BIT(3) /* Pause On */
1768 #define GMC_PAUSE_OFF BIT(2) /* Pause Off */
1769 #define GMC_RST_CLR BIT(1) /* Clear GMAC Reset */
1770 #define GMC_RST_SET BIT(0) /* Set GMAC Reset */
1773 #define GPC_SEL_BDT BIT(28) /* Select Bi-Dir. Transfer for MDC/MDIO */
1774 #define GPC_INT_POL BIT(27) /* IRQ Polarity is Active Low */
1775 #define GPC_75_OHM BIT(26) /* Use 75 Ohm Termination instead of 50 */
1776 #define GPC_DIS_FC BIT(25) /* Disable Automatic Fiber/Copper Detection */
1777 #define GPC_DIS_SLEEP BIT(24) /* Disable Energy Detect */
1778 #define GPC_HWCFG_M_3 BIT(23) /* HWCFG_MODE[3] */
1779 #define GPC_HWCFG_M_2 BIT(22) /* HWCFG_MODE[2] */
1780 #define GPC_HWCFG_M_1 BIT(21) /* HWCFG_MODE[1] */
1781 #define GPC_HWCFG_M_0 BIT(20) /* HWCFG_MODE[0] */
1782 #define GPC_ANEG_0 BIT(19) /* ANEG[0] */
1783 #define GPC_ENA_XC BIT(18) /* Enable MDI crossover */
1784 #define GPC_DIS_125 BIT(17) /* Disable 125 MHz clock */
1785 #define GPC_ANEG_3 BIT(16) /* ANEG[3] */
1786 #define GPC_ANEG_2 BIT(15) /* ANEG[2] */
1787 #define GPC_ANEG_1 BIT(14) /* ANEG[1] */
1788 #define GPC_ENA_PAUSE BIT(13) /* Enable Pause (SYM_OR_REM) */
1789 #define GPC_PHYADDR_4 BIT(12) /* Bit 4 of Phy Addr */
1790 #define GPC_PHYADDR_3 BIT(11) /* Bit 3 of Phy Addr */
1791 #define GPC_PHYADDR_2 BIT(10) /* Bit 2 of Phy Addr */
1792 #define GPC_PHYADDR_1 BIT(9) /* Bit 1 of Phy Addr */
1793 #define GPC_PHYADDR_0 BIT(8) /* Bit 0 of Phy Addr */
1794 #define GPC_RST_CLR BIT(1) /* Clear GPHY Reset */
1795 #define GPC_RST_SET BIT(0) /* Set GPHY Reset */
1799 #define GM_IS_RX_CO_OV BIT(5) /* Receive Counter Overflow IRQ */
1800 #define GM_IS_TX_CO_OV BIT(4) /* Transmit Counter Overflow IRQ */
1801 #define GM_IS_TX_FF_UR BIT(3) /* Transmit FIFO Underrun */
1802 #define GM_IS_TX_COMPL BIT(2) /* Frame Transmission Complete */
1803 #define GM_IS_RX_FF_OR BIT(1) /* Receive FIFO Overrun */
1804 #define GM_IS_RX_COMPL BIT(0) /* Frame Reception Complete */
1809 #define GMLC_RST_CLR BIT(1) /* Clear GMAC Link Reset */
1810 #define GMLC_RST_SET BIT(0) /* Set GMAC Link Reset */
2003 #define BMU_OWN BIT(31) /* OWN bit: 0=host/1=BMU */
2004 #define BMU_STF BIT(30) /* Start of Frame */
2005 #define BMU_EOF BIT(29) /* End of Frame */
2006 #define BMU_IRQ_EOB BIT(28) /* Req "End of Buffer" IRQ */
2007 #define BMU_IRQ_EOF BIT(27) /* Req "End of Frame" IRQ */
2009 #define BMU_STFWD BIT(26) /* (Tx) Store & Forward Frame */
2010 #define BMU_NO_FCS BIT(25) /* (Tx) Disable MAC FCS (CRC) generation */
2011 #define BMU_SW BIT(24) /* (Tx) 1 bit res. for SW use */
2013 #define BMU_DEV_0 BIT(26) /* (Rx) Transfer data to Dev0 */
2014 #define BMU_STAT_VAL BIT(25) /* (Rx) Rx Status Valid */
2015 #define BMU_TIST_VAL BIT(24) /* (Rx) Rx TimeStamp Valid */