Lines Matching refs:rxq

2417 	int32_t rxq;  in yge_start_port()  local
2423 rxq = port->p_rxq; in yge_start_port()
2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET); in yge_start_port()
2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT); in yge_start_port()
2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON); in yge_start_port()
2588 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80); in yge_start_port()
2590 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM); in yge_start_port()
2595 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); in yge_start_port()
2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), in yge_start_port()
2636 uint32_t rxq; in yge_set_rambuffer() local
2641 rxq = port->p_rxq; in yge_set_rambuffer()
2648 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR); in yge_set_rambuffer()
2649 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2650 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8); in yge_set_rambuffer()
2651 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2652 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8); in yge_set_rambuffer()
2662 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp); in yge_set_rambuffer()
2663 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp); in yge_set_rambuffer()
2666 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD); in yge_set_rambuffer()
2667 (void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL)); in yge_set_rambuffer()
2710 uint32_t rxq = port->p_rxq; in yge_stop_port() local
2794 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); in yge_stop_port()
2796 if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) == in yge_stop_port()
2797 CSR_READ_1(dev, RB_ADDR(rxq, Q_RL))) in yge_stop_port()
2805 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); in yge_stop_port()
2807 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(rxq, PREF_UNIT_CTRL_REG), in yge_stop_port()
2810 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET); in yge_stop_port()