115 static void dEISA_setchain(ddi_dma_cookie_t *cp, int chnl);
156 d37A_dma_valid(int chnl)  in d37A_dma_valid()  argument
159 	if (chnl == 4)  in d37A_dma_valid()
173 d37A_dma_release(int chnl)  in d37A_dma_release()  argument
176 	if (chnl == 4)  in d37A_dma_release()
179 	d37A_chnl_mode[chnl] = DMAE_TRANS_SNGL;  in d37A_dma_release()
190 d37A_dma_disable(int chnl)  in d37A_dma_disable()  argument
193 	    chnl, chan_addr[chnl].mask_reg));  in d37A_dma_disable()
195 	outb(chan_addr[chnl].mask_reg, (chnl & 3) | DMA_SETMSK);  in d37A_dma_disable()
208 d37A_dma_enable(int chnl)  in d37A_dma_enable()  argument
211 	    chnl, chan_addr[chnl].mask_reg, chnl & 3));  in d37A_dma_enable()
214 	outb(chan_addr[chnl].mask_reg, chnl & 3);  in d37A_dma_enable()
243 	int chnl, istate, nstate;  in d37A_intr()  local
248 		chnl = 0;  in d37A_intr()
253 				dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_intr()
255 				if (chnl < 4)  in d37A_intr()
256 					mask = inb(DMAC1_ALLMASK) >> (chnl);  in d37A_intr()
258 					mask = inb(DMAC2_ALLMASK) >> (chnl - 4);  in d37A_intr()
260 prom_printf("eisa: dma buffer chaining failure chnl %d!\n", chnl);  in d37A_intr()
264 			chnl++;  in d37A_intr()
267 		chnl = 0;  in d37A_intr()
269 			if ((nstate & 1) && d37A_next_cookie[chnl])  in d37A_intr()
270 				d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_intr()
271 			chnl++;  in d37A_intr()
290 dEISA_setchain(ddi_dma_cookie_t *cp, int chnl)  in dEISA_setchain()  argument
294 		    chnl, cp->dmac_address, cp->dmac_size));  in dEISA_setchain()
295 		(void) d37A_write_addr(cp->dmac_address, chnl);  in dEISA_setchain()
296 		(void) d37A_write_count(cp->dmac_size, chnl);  in dEISA_setchain()
297 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM | EISA_CMOK);  in dEISA_setchain()
302 		outb(chan_addr[chnl].scm_reg, chnl);  in dEISA_setchain()
303 		dprintf(("dEISA_setchain: chnl=%d end\n", chnl));  in dEISA_setchain()
318 d37A_prog_chan(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)  in d37A_prog_chan()  argument
320 	if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {  in d37A_prog_chan()
322 		    chnl));  in d37A_prog_chan()
333 	    chnl, (void *)dmaereqp));  in d37A_prog_chan()
336 		switch (chnl) {  in d37A_prog_chan()
344 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
359 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
366 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));  in d37A_prog_chan()
370 		chnl &= 3;  in d37A_prog_chan()
373 	d37A_dma_disable(chnl);  in d37A_prog_chan()
375 		(void) d37A_set_mode(dmaereqp, chnl);  in d37A_prog_chan()
378 		(void) d37A_write_addr(cp->dmac_address, chnl);  in d37A_prog_chan()
379 		(void) d37A_write_count(cp->dmac_size, chnl);  in d37A_prog_chan()
383 		    (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {  in d37A_prog_chan()
389 			outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_prog_chan()
391 			dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_prog_chan()
392 			d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_prog_chan()
410 d37A_dma_swsetup(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl)  in d37A_dma_swsetup()  argument
412 	if (d37A_chnl_mode[chnl] == DMAE_TRANS_CSCD) {  in d37A_dma_swsetup()
414 		    chnl));  in d37A_dma_swsetup()
419 	    chnl, (void *)dmaereqp));  in d37A_dma_swsetup()
425 	switch (chnl) {  in d37A_dma_swsetup()
432 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));  in d37A_dma_swsetup()
446 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));  in d37A_dma_swsetup()
453 		dprintf(("d37A_dma_swsetup err: chnl %d not set up.\n", chnl));  in d37A_dma_swsetup()
459 	d37A_dma_disable(chnl);  in d37A_dma_swsetup()
460 	(void) d37A_set_mode(dmaereqp, chnl);  in d37A_dma_swsetup()
462 	(void) d37A_write_addr(cp->dmac_address, chnl);  in d37A_dma_swsetup()
463 	(void) d37A_write_count(cp->dmac_size, chnl);  in d37A_dma_swsetup()
467 	    (d37A_next_cookie[chnl] = _dmae_nxcookie(chnl))) {  in d37A_dma_swsetup()
472 		outb(chan_addr[chnl].scm_reg, chnl | EISA_ENCM);  in d37A_dma_swsetup()
473 		dEISA_setchain(d37A_next_cookie[chnl], chnl);  in d37A_dma_swsetup()
474 		d37A_next_cookie[chnl] = _dmae_nxcookie(chnl);  in d37A_dma_swsetup()
490 d37A_dma_swstart(int chnl)  in d37A_dma_swstart()  argument
492 	dprintf(("d37A_dma_swstart: chnl=%d\n", chnl));  in d37A_dma_swstart()
495 	d37A_dma_enable(chnl);  in d37A_dma_swstart()
496 	outb(chan_addr[chnl].reqt_reg, DMA_SETMSK | chnl); /* set request bit */  in d37A_dma_swstart()
509 d37A_dma_stop(int chnl)  in d37A_dma_stop()  argument
511 	dprintf(("d37A_dma_stop: chnl=%d\n", chnl));  in d37A_dma_stop()
514 	d37A_dma_disable(chnl);  in d37A_dma_stop()
515 	outb(chan_addr[chnl].reqt_reg, chnl & 3);    /* reset request bit */  in d37A_dma_stop()
528 d37A_get_chan_stat(int chnl, ulong_t *addressp, int *countp)  in d37A_get_chan_stat()  argument
534 	taddr = d37A_read_addr(chnl);  in d37A_get_chan_stat()
535 	tcount = d37A_read_count(chnl);  in d37A_get_chan_stat()
542 	    chnl, taddr, tcount));  in d37A_get_chan_stat()
555 d37A_set_mode(struct ddi_dmae_req *dmaereqp, int chnl)  in d37A_set_mode()  argument
563 	mode = chnl & 3;  in d37A_set_mode()
603 	d37A_chnl_mode[chnl] = dmaereqp->der_trans;  in d37A_set_mode()
606 	    chnl, chan_addr[chnl].mode_reg, mode));  in d37A_set_mode()
607 	outb(chan_addr[chnl].mode_reg, mode);  in d37A_set_mode()
611 	emode = chnl & 3;  in d37A_set_mode()
612 	d37A_chnl_path[chnl] = dmaereqp->der_path;  in d37A_set_mode()
628 		switch (chnl) {  in d37A_set_mode()
633 			d37A_chnl_path[chnl] = DMAE_PATH_8;  in d37A_set_mode()
639 			d37A_chnl_path[chnl] = DMAE_PATH_16;  in d37A_set_mode()
645 	outb(chan_addr[chnl].emode_reg, emode);  in d37A_set_mode()
648 	    chnl, chan_addr[chnl].emode_reg, emode));  in d37A_set_mode()
663 d37A_write_addr(ulong_t paddress, int chnl)  in d37A_write_addr()  argument
667 	dprintf(("d37A_write_addr: chnl=%d address=%lx\n", chnl, paddress));  in d37A_write_addr()
669 	switch (d37A_chnl_path[chnl]) {  in d37A_write_addr()
689 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_addr()
692 	outb(chan_addr[chnl].addr_reg, adr_byte[0]);  in d37A_write_addr()
693 	outb(chan_addr[chnl].addr_reg, adr_byte[1]);  in d37A_write_addr()
694 	outb(chan_addr[chnl].page_reg, adr_byte[2]);  in d37A_write_addr()
696 	outb(chan_addr[chnl].hpage_reg, adr_byte[3]);  in d37A_write_addr()
713 d37A_read_addr(int chnl)  in d37A_read_addr()  argument
720 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_addr()
722 	adr_byte[0] = inb(chan_addr[chnl].addr_reg);  in d37A_read_addr()
723 	adr_byte[1] = inb(chan_addr[chnl].addr_reg);  in d37A_read_addr()
724 	adr_byte[2] = inb(chan_addr[chnl].page_reg);  in d37A_read_addr()
726 	adr_byte[3] = inb(chan_addr[chnl].hpage_reg);  in d37A_read_addr()
731 	switch (d37A_chnl_path[chnl]) {  in d37A_read_addr()
751 	dprintf(("d37A_read_addr: chnl=%d address=%lx.\n", chnl, paddress));  in d37A_read_addr()
765 d37A_write_count(long count, int chnl)  in d37A_write_count()  argument
769 	dprintf(("d37A_write_count: chnl=%d count=0x%lx\n", chnl, count));  in d37A_write_count()
771 	switch (d37A_chnl_path[chnl]) {  in d37A_write_count()
789 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_write_count()
792 	outb(chan_addr[chnl].cnt_reg, count_byte[0]);  in d37A_write_count()
793 	outb(chan_addr[chnl].cnt_reg, count_byte[1]);  in d37A_write_count()
795 	outb(chan_addr[chnl].hcnt_reg, count_byte[2]);  in d37A_write_count()
812 d37A_read_count(int chnl)  in d37A_read_count()  argument
819 	outb(chan_addr[chnl].ff_reg, 0);	/* set flipflop */  in d37A_read_count()
821 	count_byte[0] = inb(chan_addr[chnl].cnt_reg);  in d37A_read_count()
822 	count_byte[1] = inb(chan_addr[chnl].cnt_reg);  in d37A_read_count()
824 	count_byte[2] = inb(chan_addr[chnl].hcnt_reg);  in d37A_read_count()
836 	switch (d37A_chnl_path[chnl]) {  in d37A_read_count()
850 	dprintf(("d37A_read_count: chnl=%d count=0x%lx\n", chnl, count));  in d37A_read_count()