Lines Matching refs:tp
143 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
146 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
150 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
158 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
160 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) && in tg3_switch_clocks()
172 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val) in tg3_readphy() argument
177 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL); in tg3_readphy()
207 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_readphy()
212 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val) in tg3_writephy() argument
217 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL); in tg3_writephy()
243 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_writephy()
248 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val) in tg3_writedsp() argument
251 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr); in tg3_writedsp()
252 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_writedsp()
257 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
261 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
264 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007); in tg3_phy_set_wirespeed()
265 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); in tg3_phy_set_wirespeed()
266 tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4))); in tg3_phy_set_wirespeed()
269 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
278 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
284 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
300 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
307 tg3_readphy(tp, 0x16, &tmp32); in tg3_wait_macro_done()
317 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
330 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
332 tg3_writephy(tp, 0x16, 0x0002); in tg3_phy_write_and_check_testpat()
335 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
338 tg3_writephy(tp, 0x16, 0x0202); in tg3_phy_write_and_check_testpat()
339 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
344 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
346 tg3_writephy(tp, 0x16, 0x0082); in tg3_phy_write_and_check_testpat()
347 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
352 tg3_writephy(tp, 0x16, 0x0802); in tg3_phy_write_and_check_testpat()
353 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
361 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low); in tg3_phy_write_and_check_testpat()
362 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high); in tg3_phy_write_and_check_testpat()
363 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
371 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
372 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
373 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
383 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
390 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
392 tg3_writephy(tp, 0x16, 0x0002); in tg3_phy_reset_chanpat()
394 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
395 tg3_writephy(tp, 0x16, 0x0202); in tg3_phy_reset_chanpat()
396 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
403 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
412 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
419 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
421 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
424 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
428 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig); in tg3_phy_reset_5703_4_5()
429 tg3_writephy(tp, MII_TG3_CTRL, in tg3_phy_reset_5703_4_5()
434 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); in tg3_phy_reset_5703_4_5()
437 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); in tg3_phy_reset_5703_4_5()
438 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); in tg3_phy_reset_5703_4_5()
440 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
445 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
449 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); in tg3_phy_reset_5703_4_5()
450 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); in tg3_phy_reset_5703_4_5()
452 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
453 tg3_writephy(tp, 0x16, 0x0000); in tg3_phy_reset_5703_4_5()
455 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); in tg3_phy_reset_5703_4_5()
457 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); in tg3_phy_reset_5703_4_5()
459 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
461 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
469 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
474 err = tg3_readphy(tp, MII_BMSR, &phy_status); in tg3_phy_reset()
475 err |= tg3_readphy(tp, MII_BMSR, &phy_status); in tg3_phy_reset()
479 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || in tg3_phy_reset()
480 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || in tg3_phy_reset()
481 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { in tg3_phy_reset()
482 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
487 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
491 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
495 static void tg3_set_power_state_0(struct tg3 *tp) in tg3_set_power_state_0() argument
498 int pm = tp->pm_cap; in tg3_set_power_state_0()
503 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_set_power_state_0()
505 pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control); in tg3_set_power_state_0()
510 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control); in tg3_set_power_state_0()
512 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_set_power_state_0()
519 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
521 if (!tp->carrier_ok) { in tg3_link_report()
525 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
527 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
529 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
531 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "", in tg3_link_report()
532 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "", in tg3_link_report()
533 (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : ""); in tg3_link_report()
537 #define tg3_link_report(tp) argument
540 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv) in tg3_setup_flow_control() argument
565 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE); in tg3_setup_flow_control()
566 tp->tg3_flags |= new_tg3_flags; in tg3_setup_flow_control()
569 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
571 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
574 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
576 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
581 struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex) in tg3_aux_stat_to_speed_duplex()
599 static int tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
603 tp->link_config.advertising = in tg3_phy_copper_begin()
609 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) { in tg3_phy_copper_begin()
610 tp->link_config.advertising &= in tg3_phy_copper_begin()
615 if (tp->link_config.advertising & ADVERTISED_10baseT_Half) { in tg3_phy_copper_begin()
618 if (tp->link_config.advertising & ADVERTISED_10baseT_Full) { in tg3_phy_copper_begin()
621 if (tp->link_config.advertising & ADVERTISED_100baseT_Half) { in tg3_phy_copper_begin()
624 if (tp->link_config.advertising & ADVERTISED_100baseT_Full) { in tg3_phy_copper_begin()
627 tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_copper_begin()
629 if (tp->link_config.advertising & in tg3_phy_copper_begin()
632 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) { in tg3_phy_copper_begin()
635 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) { in tg3_phy_copper_begin()
638 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && in tg3_phy_copper_begin()
639 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || in tg3_phy_copper_begin()
640 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_begin()
644 tg3_writephy(tp, MII_TG3_CTRL, new_adv); in tg3_phy_copper_begin()
646 tg3_writephy(tp, MII_TG3_CTRL, 0); in tg3_phy_copper_begin()
649 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); in tg3_phy_copper_begin()
654 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
659 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20); in tg3_init_5401phy_dsp()
661 err |= tg3_writedsp(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
662 err |= tg3_writedsp(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
663 err |= tg3_writedsp(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
664 err |= tg3_writedsp(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
665 err |= tg3_writedsp(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
672 static int tg3_setup_copper_phy(struct tg3 *tp) in tg3_setup_copper_phy() argument
681 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_setup_copper_phy()
682 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
684 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); in tg3_setup_copper_phy()
689 if ( ( (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || in tg3_setup_copper_phy()
690 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || in tg3_setup_copper_phy()
691 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) && in tg3_setup_copper_phy()
692 (tp->carrier_ok)) { in tg3_setup_copper_phy()
693 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
694 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
696 tg3_phy_reset(tp); in tg3_setup_copper_phy()
699 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { in tg3_setup_copper_phy()
700 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
701 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
703 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) in tg3_setup_copper_phy()
707 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
711 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
714 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
721 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && in tg3_setup_copper_phy()
723 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
724 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
726 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
731 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
732 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
734 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
735 tg3_writephy(tp, 0x1c, 0x8c68); in tg3_setup_copper_phy()
736 tg3_writephy(tp, 0x1c, 0x8d68); in tg3_setup_copper_phy()
737 tg3_writephy(tp, 0x1c, 0x8c68); in tg3_setup_copper_phy()
741 tg3_readphy(tp, MII_TG3_ISTAT, &dummy); in tg3_setup_copper_phy()
742 tg3_readphy(tp, MII_TG3_ISTAT, &dummy); in tg3_setup_copper_phy()
744 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
746 if (tp->led_mode == led_mode_three_link) in tg3_setup_copper_phy()
747 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
750 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
754 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
755 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
760 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
763 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
768 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
769 &tp->link_config.active_speed, in tg3_setup_copper_phy()
770 &tp->link_config.active_duplex); in tg3_setup_copper_phy()
771 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
772 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
781 tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl); in tg3_setup_copper_phy()
792 (tp->link_config.active_duplex == DUPLEX_FULL)) { in tg3_setup_copper_phy()
795 tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_copper_phy()
798 tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_copper_phy()
807 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_copper_phy()
814 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
816 tg3_readphy(tp, MII_BMSR, &tmp); in tg3_setup_copper_phy()
817 tg3_readphy(tp, MII_BMSR, &tmp); in tg3_setup_copper_phy()
822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
824 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
825 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
826 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
828 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
832 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
833 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
834 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
836 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { in tg3_setup_copper_phy()
838 if ((tp->led_mode == led_mode_link10) || in tg3_setup_copper_phy()
840 tp->link_config.active_speed == SPEED_10)) in tg3_setup_copper_phy()
841 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
844 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
852 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && in tg3_setup_copper_phy()
853 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
854 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
855 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
858 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && in tg3_setup_copper_phy()
865 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
866 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || in tg3_setup_copper_phy()
867 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
876 if (current_link_up != tp->carrier_ok) { in tg3_setup_copper_phy()
877 tp->carrier_ok = current_link_up; in tg3_setup_copper_phy()
878 tg3_link_report(tp); in tg3_setup_copper_phy()
952 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
1031 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
1032 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
1055 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
1056 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
1070 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
1071 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
1155 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
1156 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
1196 static int tg3_setup_fiber_phy(struct tg3 *tp) in tg3_setup_fiber_phy() argument
1205 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE | in tg3_setup_fiber_phy()
1207 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
1208 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
1210 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
1211 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
1212 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
1215 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) || in tg3_setup_fiber_phy()
1218 tg3_writephy(tp, 0x16, 0x8007); in tg3_setup_fiber_phy()
1221 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_setup_fiber_phy()
1227 tg3_writephy(tp, 0x10, 0x8411); in tg3_setup_fiber_phy()
1230 tg3_writephy(tp, 0x11, 0x0a10); in tg3_setup_fiber_phy()
1232 tg3_writephy(tp, 0x18, 0x00a0); in tg3_setup_fiber_phy()
1233 tg3_writephy(tp, 0x16, 0x41ff); in tg3_setup_fiber_phy()
1236 tg3_writephy(tp, 0x13, 0x0400); in tg3_setup_fiber_phy()
1238 tg3_writephy(tp, 0x13, 0x0000); in tg3_setup_fiber_phy()
1240 tg3_writephy(tp, 0x11, 0x0a50); in tg3_setup_fiber_phy()
1242 tg3_writephy(tp, 0x11, 0x0a10); in tg3_setup_fiber_phy()
1250 tg3_writephy(tp, 0x10, 0x8011); in tg3_setup_fiber_phy()
1258 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) { in tg3_setup_fiber_phy()
1269 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_phy()
1272 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in tg3_setup_fiber_phy()
1278 status = tg3_fiber_aneg_smachine(tp, &aninfo); in tg3_setup_fiber_phy()
1286 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_setup_fiber_phy()
1287 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
1302 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_phy()
1304 tp->tg3_flags |= in tg3_setup_fiber_phy()
1327 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_fiber_phy()
1328 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
1330 tp->hw_status->status = in tg3_setup_fiber_phy()
1332 (tp->hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
1348 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
1349 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
1351 tp->link_config.active_speed = SPEED_INVALID; in tg3_setup_fiber_phy()
1352 tp->link_config.active_duplex = DUPLEX_INVALID; in tg3_setup_fiber_phy()
1355 if (current_link_up != tp->carrier_ok) { in tg3_setup_fiber_phy()
1356 tp->carrier_ok = current_link_up; in tg3_setup_fiber_phy()
1357 tg3_link_report(tp); in tg3_setup_fiber_phy()
1360 tp->tg3_flags & (TG3_FLAG_RX_PAUSE | in tg3_setup_fiber_phy()
1363 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
1364 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
1365 tg3_link_report(tp); in tg3_setup_fiber_phy()
1369 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY); in tg3_setup_fiber_phy()
1370 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { in tg3_setup_fiber_phy()
1371 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
1381 static int tg3_setup_phy(struct tg3 *tp) in tg3_setup_phy() argument
1385 if (tp->phy_id == PHY_ID_SERDES) { in tg3_setup_phy()
1386 err = tg3_setup_fiber_phy(tp); in tg3_setup_phy()
1388 err = tg3_setup_copper_phy(tp); in tg3_setup_phy()
1391 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
1392 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
1412 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit) in tg3_stop_block() argument
1417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { in tg3_stop_block()
1453 static int tg3_abort_hw(struct tg3 *tp) in tg3_abort_hw() argument
1457 tg3_disable_ints(tp); in tg3_abort_hw()
1459 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
1460 tw32_carefully(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
1462 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE); in tg3_abort_hw()
1463 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE); in tg3_abort_hw()
1464 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE); in tg3_abort_hw()
1465 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE); in tg3_abort_hw()
1466 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE); in tg3_abort_hw()
1467 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE); in tg3_abort_hw()
1469 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE); in tg3_abort_hw()
1470 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE); in tg3_abort_hw()
1471 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); in tg3_abort_hw()
1472 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE); in tg3_abort_hw()
1473 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); in tg3_abort_hw()
1474 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE); in tg3_abort_hw()
1478 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
1479 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
1481 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
1482 tw32_carefully(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
1495 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE); in tg3_abort_hw()
1496 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE); in tg3_abort_hw()
1497 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE); in tg3_abort_hw()
1502 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE); in tg3_abort_hw()
1503 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE); in tg3_abort_hw()
1507 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
1513 static void tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
1517 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) { in tg3_chip_reset()
1522 if (tp->tg3_flags & TG3_FLAG_NVRAM) { in tg3_chip_reset()
1539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) in tg3_chip_reset()
1548 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
1553 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_chip_reset()
1554 tp->misc_host_ctrl); in tg3_chip_reset()
1558 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && in tg3_chip_reset()
1559 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) in tg3_chip_reset()
1561 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_chip_reset()
1563 pci_restore_state(tp->pdev, tp->pci_cfg_state); in tg3_chip_reset()
1566 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val); in tg3_chip_reset()
1568 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); in tg3_chip_reset()
1572 if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) && in tg3_chip_reset()
1573 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { in tg3_chip_reset()
1574 tp->pci_clock_ctrl |= in tg3_chip_reset()
1576 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
1579 tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_chip_reset()
1582 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1584 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { in tg3_stop_fw()
1602 static int tg3_restart_fw(struct tg3 *tp, uint32_t state) in tg3_restart_fw() argument
1617 !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) { in tg3_restart_fw()
1622 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { in tg3_restart_fw()
1629 static int tg3_halt(struct tg3 *tp) in tg3_halt() argument
1631 tg3_stop_fw(tp); in tg3_halt()
1632 tg3_abort_hw(tp); in tg3_halt()
1633 tg3_chip_reset(tp); in tg3_halt()
1634 return tg3_restart_fw(tp, DRV_STATE_UNLOAD); in tg3_halt()
1637 static void __tg3_set_mac_addr(struct tg3 *tp) in __tg3_set_mac_addr() argument
1642 addr_high = ((tp->nic->node_addr[0] << 8) | in __tg3_set_mac_addr()
1643 tp->nic->node_addr[1]); in __tg3_set_mac_addr()
1644 addr_low = ((tp->nic->node_addr[2] << 24) | in __tg3_set_mac_addr()
1645 (tp->nic->node_addr[3] << 16) | in __tg3_set_mac_addr()
1646 (tp->nic->node_addr[4] << 8) | in __tg3_set_mac_addr()
1647 (tp->nic->node_addr[5] << 0)); in __tg3_set_mac_addr()
1653 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && in __tg3_set_mac_addr()
1654 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && in __tg3_set_mac_addr()
1655 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) { in __tg3_set_mac_addr()
1661 addr_high = (tp->nic->node_addr[0] + in __tg3_set_mac_addr()
1662 tp->nic->node_addr[1] + in __tg3_set_mac_addr()
1663 tp->nic->node_addr[2] + in __tg3_set_mac_addr()
1664 tp->nic->node_addr[3] + in __tg3_set_mac_addr()
1665 tp->nic->node_addr[4] + in __tg3_set_mac_addr()
1666 tp->nic->node_addr[5]) & in __tg3_set_mac_addr()
1671 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr, in tg3_set_bdinfo() argument
1684 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_set_bdinfo()
1690 static void tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
1696 tp->rx_std = &tg3_bss.rx_std[0]; in tg3_init_rings()
1697 tp->rx_rcb = &tg3_bss.rx_rcb[0]; in tg3_init_rings()
1698 tp->tx_ring = &tg3_bss.tx_ring[0]; in tg3_init_rings()
1699 tp->hw_status = &tg3_bss.hw_status; in tg3_init_rings()
1700 tp->hw_stats = &tg3_bss.hw_stats; in tg3_init_rings()
1701 tp->mac_mode = 0; in tg3_init_rings()
1718 rxd = &tp->rx_std[i]; in tg3_init_rings()
1742 static int tg3_setup_hw(struct tg3 *tp) in tg3_setup_hw() argument
1748 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { in tg3_setup_hw()
1753 tg3_disable_ints(tp); in tg3_setup_hw()
1758 tg3_set_power_state_0(tp); in tg3_setup_hw()
1760 tg3_switch_clocks(tp); in tg3_setup_hw()
1767 tg3_stop_fw(tp); in tg3_setup_hw()
1771 tg3_chip_reset(tp); in tg3_setup_hw()
1773 tw32(GRC_MODE, tp->grc_mode); /* Redundant? */ in tg3_setup_hw()
1775 err = tg3_restart_fw(tp, DRV_STATE_START); in tg3_setup_hw()
1779 if (tp->phy_id == PHY_ID_SERDES) { in tg3_setup_hw()
1780 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_setup_hw()
1782 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_setup_hw()
1789 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_setup_hw()
1790 tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_setup_hw()
1792 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && in tg3_setup_hw()
1793 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { in tg3_setup_hw()
1804 tg3_init_rings(tp); in tg3_setup_hw()
1807 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
1819 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_setup_hw()
1821 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_setup_hw()
1825 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_setup_hw()
1826 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_setup_hw()
1827 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM; in tg3_setup_hw()
1830 tp->grc_mode | in tg3_setup_hw()
1838 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
1840 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) in tg3_setup_hw()
1847 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) { in tg3_setup_hw()
1849 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_setup_hw()
1851 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_setup_hw()
1853 tp->bufmgr_config.mbuf_high_water); in tg3_setup_hw()
1856 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_setup_hw()
1858 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_setup_hw()
1860 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_setup_hw()
1863 tp->bufmgr_config.dma_low_water); in tg3_setup_hw()
1865 tp->bufmgr_config.dma_high_water); in tg3_setup_hw()
1933 virt_to_bus(tp->rx_std)); in tg3_setup_hw()
1934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { in tg3_setup_hw()
1946 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
1952 tp->tx_prod = 0; in tg3_setup_hw()
1956 tg3_set_bdinfo(tp, in tg3_setup_hw()
1958 virt_to_bus(tp->tx_ring), in tg3_setup_hw()
1965 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
1972 tp->rx_rcb_ptr = 0; in tg3_setup_hw()
1975 tg3_set_bdinfo(tp, in tg3_setup_hw()
1977 virt_to_bus(tp->rx_rcb), in tg3_setup_hw()
1981 tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING; in tg3_setup_hw()
1983 tp->rx_std_ptr); in tg3_setup_hw()
1988 __tg3_set_mac_addr(tp); in tg3_setup_hw()
1998 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) in tg3_setup_hw()
2000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { in tg3_setup_hw()
2001 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { in tg3_setup_hw()
2003 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { in tg3_setup_hw()
2017 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_setup_hw()
2019 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_setup_hw()
2021 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_setup_hw()
2022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) in tg3_setup_hw()
2023 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_setup_hw()
2025 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_setup_hw()
2030 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
2039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) && in tg3_setup_hw()
2041 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { in tg3_setup_hw()
2046 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { in tg3_setup_hw()
2048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { in tg3_setup_hw()
2051 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { in tg3_setup_hw()
2054 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) in tg3_setup_hw()
2055 val |= (tp->split_mode_max_reqs << in tg3_setup_hw()
2137 virt_to_bus(tp->hw_stats)); in tg3_setup_hw()
2139 virt_to_bus(tp->hw_status)); in tg3_setup_hw()
2140 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { in tg3_setup_hw()
2145 tp->tx_mode = TX_MODE_ENABLE; in tg3_setup_hw()
2146 tw32_carefully(MAC_TX_MODE, tp->tx_mode); in tg3_setup_hw()
2148 tp->rx_mode = RX_MODE_ENABLE; in tg3_setup_hw()
2149 tw32_carefully(MAC_RX_MODE, tp->rx_mode); in tg3_setup_hw()
2151 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_setup_hw()
2152 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_setup_hw()
2156 if (tp->phy_id == PHY_ID_SERDES) { in tg3_setup_hw()
2159 tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */ in tg3_setup_hw()
2160 tw32_carefully(MAC_RX_MODE, tp->rx_mode); in tg3_setup_hw()
2162 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) in tg3_setup_hw()
2171 err = tg3_setup_phy(tp); in tg3_setup_hw()
2181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) in tg3_setup_hw()
2185 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) in tg3_setup_hw()
2214 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
2227 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && in tg3_nvram_init()
2228 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { in tg3_nvram_init()
2231 tp->tg3_flags |= TG3_FLAG_NVRAM; in tg3_nvram_init()
2234 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; in tg3_nvram_init()
2241 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); in tg3_nvram_init()
2247 struct tg3 *tp __unused, uint32_t offset, uint32_t *val) in tg3_nvram_read_using_eeprom()
2282 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val) in tg3_nvram_read() argument
2286 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) in tg3_nvram_read()
2287 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
2289 if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) in tg3_nvram_read()
2374 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
2383 tp->phy_id = PHY_ID_INVALID; in tg3_phy_probe()
2386 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) && in tg3_phy_probe()
2387 (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) { in tg3_phy_probe()
2388 tp->phy_id = subsys_id_to_phy_id[i].phy_id; in tg3_phy_probe()
2401 tp->nic_sram_data_cfg = nic_cfg; in tg3_phy_probe()
2435 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || in tg3_phy_probe()
2436 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || in tg3_phy_probe()
2437 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) && in tg3_phy_probe()
2439 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; in tg3_phy_probe()
2443 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; in tg3_phy_probe()
2445 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP; in tg3_phy_probe()
2453 err = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
2454 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
2463 tp->phy_id = hw_phy_id; in tg3_phy_probe()
2469 if (tp->phy_id == PHY_ID_INVALID) { in tg3_phy_probe()
2473 tp->phy_id = eeprom_phy_id; in tg3_phy_probe()
2477 err = tg3_phy_reset(tp); in tg3_phy_probe()
2481 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || in tg3_phy_probe()
2482 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { in tg3_phy_probe()
2488 err = tg3_writephy(tp, MII_ADVERTISE, in tg3_phy_probe()
2499 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) in tg3_phy_probe()
2502 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl); in tg3_phy_probe()
2503 err |= tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
2507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { in tg3_phy_probe()
2508 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); in tg3_phy_probe()
2509 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); in tg3_phy_probe()
2510 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); in tg3_phy_probe()
2513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { in tg3_phy_probe()
2514 tg3_writephy(tp, 0x1c, 0x8d68); in tg3_phy_probe()
2515 tg3_writephy(tp, 0x1c, 0x8d68); in tg3_phy_probe()
2519 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
2521 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { in tg3_phy_probe()
2522 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
2529 if (tp->phy_id == PHY_ID_SERDES) { in tg3_phy_probe()
2530 tp->led_mode = led_mode_three_link; in tg3_phy_probe()
2532 else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) { in tg3_phy_probe()
2533 tp->led_mode = led_mode_link10; in tg3_phy_probe()
2535 tp->led_mode = led_mode_three_link; in tg3_phy_probe()
2538 tp->led_mode = eeprom_led_mode; in tg3_phy_probe()
2541 if (tp->phy_id == PHY_ID_SERDES) in tg3_phy_probe()
2542 tp->link_config.advertising = in tg3_phy_probe()
2547 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) in tg3_phy_probe()
2548 tp->link_config.advertising &= in tg3_phy_probe()
2556 static void tg3_read_partno(struct tg3 *tp) in tg3_read_partno() argument
2564 if (tg3_nvram_read(tp, 0x100 + i, &tmp)) in tg3_read_partno()
2600 memcpy(tp->board_part_number, in tg3_read_partno()
2614 memcpy(tp->board_part_number, "none", sizeof("none")); in tg3_read_partno()
2620 static int tg3_get_invariants(struct tg3 *tp) in tg3_get_invariants() argument
2629 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor); in tg3_get_invariants()
2630 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device); in tg3_get_invariants()
2652 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
2656 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
2664 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg); in tg3_get_invariants()
2666 tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT); in tg3_get_invariants()
2669 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
2671 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
2672 tp->misc_host_ctrl); in tg3_get_invariants()
2674 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency); in tg3_get_invariants()
2676 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64); in tg3_get_invariants()
2679 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg); in tg3_get_invariants()
2690 tp->tg3_flags |= TG3_FLAG_PCIX_MODE; in tg3_get_invariants()
2700 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; in tg3_get_invariants()
2702 tp->tg3_flags |= TG3_FLAG_PCI_32BIT; in tg3_get_invariants()
2705 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
2708 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
2712 tg3_set_power_state_0(tp); in tg3_get_invariants()
2719 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || in tg3_get_invariants()
2720 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && in tg3_get_invariants()
2721 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
2722 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) { in tg3_get_invariants()
2723 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
2742 tw32_carefully(MAC_MI_MODE, tp->mi_mode); in tg3_get_invariants()
2745 tw32(GRC_MODE, tp->grc_mode); in tg3_get_invariants()
2747 tg3_switch_clocks(tp); in tg3_get_invariants()
2757 tg3_nvram_init(tp); in tg3_get_invariants()
2767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && in tg3_get_invariants()
2769 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE; in tg3_get_invariants()
2770 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ; in tg3_get_invariants()
2773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && in tg3_get_invariants()
2776 tp->tg3_flags2 |= TG3_FLG2_IS_5788; in tg3_get_invariants()
2779 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) && in tg3_get_invariants()
2781 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && in tg3_get_invariants()
2782 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) && in tg3_get_invariants()
2783 ((tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901) || in tg3_get_invariants()
2784 (tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901_2)))) { in tg3_get_invariants()
2785 tp->tg3_flags |= TG3_FLAG_10_100_ONLY; in tg3_get_invariants()
2788 err = tg3_phy_probe(tp); in tg3_get_invariants()
2793 tg3_read_partno(tp); in tg3_get_invariants()
2811 static int tg3_get_device_address(struct tg3 *tp) in tg3_get_device_address() argument
2813 struct nic *nic = tp->nic; in tg3_get_device_address()
2816 if (PCI_FUNC(tp->pdev->devfn) == 0) in tg3_get_device_address()
2834 else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
2835 !tg3_nvram_read(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
2860 static int tg3_setup_dma(struct tg3 *tp) in tg3_setup_dma() argument
2864 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) { in tg3_setup_dma()
2865 tp->dma_rwctrl = in tg3_setup_dma()
2871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { in tg3_setup_dma()
2872 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT); in tg3_setup_dma()
2875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) in tg3_setup_dma()
2876 tp->dma_rwctrl = in tg3_setup_dma()
2883 tp->dma_rwctrl = in tg3_setup_dma()
2891 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || in tg3_setup_dma()
2892 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) { in tg3_setup_dma()
2896 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_setup_dma()
2901 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || in tg3_setup_dma()
2902 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) { in tg3_setup_dma()
2903 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT); in tg3_setup_dma()
2906 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_setup_dma()
2908 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_setup_dma()
2913 static void tg3_init_link_config(struct tg3 *tp) in tg3_init_link_config() argument
2915 tp->link_config.advertising = in tg3_init_link_config()
2920 tp->carrier_ok = 0; in tg3_init_link_config()
2921 tp->link_config.active_speed = SPEED_INVALID; in tg3_init_link_config()
2922 tp->link_config.active_duplex = DUPLEX_INVALID; in tg3_init_link_config()
2927 static const char * tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
2929 switch (tp->phy_id & PHY_ID_MASK) { in tg3_phy_string()
2946 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
2951 if (tp->phy_id == PHY_ID_SERDES) { in tg3_poll_link()
2952 if (tp->carrier_ok? in tg3_poll_link()
2955 tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK); in tg3_poll_link()
2956 tw32_carefully(MAC_MODE, tp->mac_mode); in tg3_poll_link()
2958 tg3_setup_phy(tp); in tg3_poll_link()
2963 tg3_setup_phy(tp); in tg3_poll_link()
2971 static void tg3_ack_irqs(struct tg3 *tp) in tg3_ack_irqs() argument
2973 if (tp->hw_status->status & SD_STATUS_UPDATED) { in tg3_ack_irqs()
2988 tp->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_ack_irqs()
2998 struct tg3 *tp = &tg3; in tg3_poll() local
3003 if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) in tg3_poll()
3006 tg3_ack_irqs(tp); in tg3_poll()
3008 if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) { in tg3_poll()
3011 desc = &tp->rx_rcb[tp->rx_rcb_ptr]; in tg3_poll()
3019 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE; in tg3_poll()
3022 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr); in tg3_poll()
3026 tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE; in tg3_poll()
3027 tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr); in tg3_poll()
3030 tg3_poll_link(tp); in tg3_poll()
3038 static void tg3_set_txd(struct tg3 *tp, int entry,
3042 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3068 struct tg3 *tp; in tg3_transmit() local
3073 tp = &tg3; in tg3_transmit()
3075 entry = tp->tx_prod; in tg3_transmit()
3076 while((tp->hw_status->idx[0].tx_consumer != entry) && in tg3_transmit()
3077 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) { in tg3_transmit()
3082 tg3_halt(tp); in tg3_transmit()
3083 tg3_setup_hw(tp); in tg3_transmit()
3099 txd = &tp->tx_ring[entry]; in tg3_transmit()
3112 tp->tx_prod = entry; in tg3_transmit()
3120 struct tg3 *tp = &tg3; in tg3_disable() local
3131 tg3_halt(tp); in tg3_disable()
3132 tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL); in tg3_disable()
3133 tp->carrier_ok = 0; in tg3_disable()
3134 iounmap((void *)tp->regs); in tg3_disable()
3159 struct tg3 *tp = &tg3; in tg3_probe() local
3166 memset(tp, 0, sizeof(*tp)); in tg3_probe()
3186 tp->pdev = pdev; in tg3_probe()
3187 tp->nic = nic; in tg3_probe()
3188 tp->pm_cap = pm_cap; in tg3_probe()
3189 tp->rx_mode = 0; in tg3_probe()
3190 tp->tx_mode = 0; in tg3_probe()
3191 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_probe()
3192 tp->tg3_flags = 0 & ~TG3_FLAG_INIT_COMPLETE; in tg3_probe()
3198 tp->misc_host_ctrl = in tg3_probe()
3210 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_probe()
3213 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_probe()
3215 tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len); in tg3_probe()
3216 if (tp->regs == 0UL) { in tg3_probe()
3221 tg3_init_link_config(tp); in tg3_probe()
3223 err = tg3_get_invariants(tp); in tg3_probe()
3229 err = tg3_get_device_address(tp); in tg3_probe()
3236 tg3_setup_dma(tp); in tg3_probe()
3242 pci_save_state(tp->pdev, tp->pci_cfg_state); in tg3_probe()
3245 tp->board_part_number, in tg3_probe()
3246 tp->pci_chip_rev_id, in tg3_probe()
3247 tg3_phy_string(tp), in tg3_probe()
3248 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""), in tg3_probe()
3249 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ? in tg3_probe()
3250 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") : in tg3_probe()
3251 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")), in tg3_probe()
3252 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit")); in tg3_probe()
3255 err = tg3_setup_hw(tp); in tg3_probe()
3259 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; in tg3_probe()
3262 tg3_poll_link(tp); in tg3_probe()
3263 for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) { in tg3_probe()
3265 tg3_poll_link(tp); in tg3_probe()
3267 if (!tp->carrier_ok){ in tg3_probe()
3280 iounmap((void *)tp->regs); in tg3_probe()