Lines Matching refs:ldx
519 ldx [%sp + V9BIAS64 + 0], %l0 ;\
520 ldx [%sp + V9BIAS64 + 8], %l1 ;\
521 ldx [%sp + V9BIAS64 + 16], %l2 ;\
522 ldx [%sp + V9BIAS64 + 24], %l3 ;\
523 ldx [%sp + V9BIAS64 + 32], %l4 ;\
524 ldx [%sp + V9BIAS64 + 40], %l5 ;\
525 ldx [%sp + V9BIAS64 + 48], %l6 ;\
526 ldx [%sp + V9BIAS64 + 56], %l7 ;\
527 ldx [%sp + V9BIAS64 + 64], %i0 ;\
528 ldx [%sp + V9BIAS64 + 72], %i1 ;\
529 ldx [%sp + V9BIAS64 + 80], %i2 ;\
530 ldx [%sp + V9BIAS64 + 88], %i3 ;\
531 ldx [%sp + V9BIAS64 + 96], %i4 ;\
532 ldx [%sp + V9BIAS64 + 104], %i5 ;\
533 ldx [%sp + V9BIAS64 + 112], %i6 ;\
534 ldx [%sp + V9BIAS64 + 120], %i7 ;\
838 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\
839 ldx [%g3 + MMFSA_I_CTX], %g3 ;\
858 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\
861 ldx [%g3 + MMFSA_D_CTX], %g3 ;\
872 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\
875 ldx [%g3 + MMFSA_D_CTX], %g3 ;\
1061 ldx [%g4 + %g1], %g1 ;\
1068 ldx [%g4 + %g1], %g1 ;\
1380 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */
1381 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */
1490 ldx [%g1 + CPU_TMP1], %g2
1653 ldx [%g1 + CPU_TMP1], %g2
1821 ldx [%g7], %g5
1834 ldx [%g7], %g5
2209 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2228 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2386 ldx [%g6 + MMFSA_D_ADDR], %g6
2393 ldx [%g6 + MMFSA_D_TYPE], %g7 ! XXXQ should be a MMFSA_F_ constant?
2394 ldx [%g6 + MMFSA_D_CTX], %g6
2456 ldx [%g7 + MMFSA_D_ADDR], %g6
2457 ldx [%g7 + MMFSA_D_CTX], %g7
2517 ldx [%g6 + MMFSA_D_ADDR], %g4
2519 ldx [%g6 + MMFSA_D_CTX], %g4
2521 ldx [%g6 + MMFSA_D_TYPE], %g4
2542 ldx [%g6 + MMFSA_I_ADDR], %g4
2544 ldx [%g6 + MMFSA_I_CTX], %g4
2546 ldx [%g6 + MMFSA_I_TYPE], %g4
2634 ldx [%g6 + %g4], %g6
2640 ldx [%g6 + %g4], %g6
2676 ldx [%g6 + %g4], %g6
2704 ldx [%g3 + MMFSA_D_ADDR], %g2
2707 ldx [%g3 + MMFSA_D_CTX], %g3
2721 ldx [%g3 + MMFSA_D_ADDR], %g2
2724 ldx [%g3 + MMFSA_D_CTX], %g3
2735 ldx [%g3 + MMFSA_D_ADDR], %g2
2736 ldx [%g3 + MMFSA_D_TYPE], %g1
2737 ldx [%g3 + MMFSA_D_CTX], %g4