Lines Matching refs:g1
122 set trap, %g1 ;\
132 mov PTL1_BAD_TRAP, %g1 ;\
156 set trap, %g1 ;\
176 set (which), %g1 ;\
222 rdpr %tstate, %g1 ;\
223 btst TSTATE_PRIV, %g1 ;\
226 set trap, %g1 ;\
237 set dtrace_pid_probe, %g1 ;\
244 set dtrace_return_probe, %g1 ;\
324 mov 4, %g1 ;\
325 sta %l1, [%sp + %g1]asi_num ;\
332 sta %l5, [%g4 + %g1]asi_num ;\
337 sta %i1, [%g4 + %g1]asi_num ;\
342 sta %i5, [%g4 + %g1]asi_num ;\
399 mov 4, %g1 ;\
402 lda [%sp + %g1]asi_num, %l1 ;\
408 lda [%g4 + %g1]asi_num, %l5 ;\
413 lda [%g4 + %g1]asi_num, %i1 ;\
418 lda [%g4 + %g1]asi_num, %i5 ;\
477 mov 0 + V9BIAS64, %g1 ;\
478 2: stxa %l0, [%sp + %g1]asi_num ;\
486 stxa %l4, [%g5 + %g1]asi_num ;\
491 stxa %i0, [%g5 + %g1]asi_num ;\
496 stxa %i4, [%g5 + %g1]asi_num ;\
548 mov V9BIAS64 + 0, %g1 ;\
550 ldxa [%sp + %g1]asi_num, %l0 ;\
558 ldxa [%g5 + %g1]asi_num, %l4 ;\
563 ldxa [%g5 + %g1]asi_num, %i0 ;\
568 ldxa [%g5 + %g1]asi_num, %i4 ;\
634 mov 4, %g1 ;\
635 sta %l1, [%sp + %g1]asi_num ;\
642 sta %l5, [%g4 + %g1]asi_num ;\
647 sta %i1, [%g4 + %g1]asi_num ;\
652 sta %i5, [%g4 + %g1]asi_num ;\
663 mov 0 + V9BIAS64, %g1 ;\
664 stxa %l0, [%sp + %g1]asi_num ;\
672 stxa %l4, [%g5 + %g1]asi_num ;\
677 stxa %i0, [%g5 + %g1]asi_num ;\
682 stxa %i4, [%g5 + %g1]asi_num ;\
725 set trap, %g1 ;\
814 mov PTL1_BAD_WATCHDOG, %g1 ;\
823 mov PTL1_BAD_RED, %g1 ;\
838 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\
841 or %g3, %g1, %g3 ;\
843 mov T_INSTR_EXCEPTION, %g1 ;\
860 mov MMFSA_F_PRVACT, %g1 ;\
864 or %g3, %g1, %g3 ;\
874 mov MMFSA_F_UNALIGN, %g1 ;\
878 or %g3, %g1, %g3 /* SFSR */ ;\
935 mov SCRATCHPAD_UTSBREG2, %g1 ;\
936 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\
937 brgez,pn %g1, sfmmu_udtlb_slowpath /* branch if 2 TSBs */ ;\
939 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
979 mov SCRATCHPAD_UTSBREG2, %g1 ;\
980 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\
981 brgez,pn %g1, sfmmu_uitlb_slowpath /* branch if 2 TSBs */ ;\
983 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\
1047 stna %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\
1053 or %g6, (ttextra), %g1 ;\
1054 stha %g1, [%g3 + TRAP_ENT_TT]%asi ;\
1056 mov MMFSA_D_ADDR, %g1 ;\
1058 move %xcc, MMFSA_I_ADDR, %g1 ;\
1060 move %xcc, MMFSA_I_ADDR, %g1 ;\
1061 ldx [%g4 + %g1], %g1 ;\
1062 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* fault addr */ ;\
1063 mov MMFSA_D_CTX, %g1 ;\
1065 move %xcc, MMFSA_I_CTX, %g1 ;\
1067 move %xcc, MMFSA_I_CTX, %g1 ;\
1068 ldx [%g4 + %g1], %g1 ;\
1069 stna %g1, [%g3 + TRAP_ENT_TR]%asi ;\
1254 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic);
1388 set trap, %g1
1394 rdpr %tstate, %g1
1395 btst TSTATE_PRIV, %g1
1398 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1399 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1400 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1401 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1417 mov T_ALIGNMENT, %g1
1420 rdpr %tstate, %g1
1421 btst TSTATE_PRIV, %g1
1424 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1425 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1426 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1427 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1434 mov T_PRIV_INSTR, %g1
1450 or %g3, %g1, %g3
1451 set trap, %g1
1456 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1457 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1461 mov PTL1_BAD_FPTRAP, %g1
1463 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1464 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1479 set fp_disabled, %g1
1484 rdpr %tstate, %g1
1485 btst TSTATE_PRIV, %g1
1487 mov PTL1_BAD_FPTRAP, %g1
1488 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1489 stx %fsr, [%g1 + CPU_TMP1]
1490 ldx [%g1 + CPU_TMP1], %g2
1491 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1492 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1493 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1500 set _fp_ieee_exception, %g1
1510 set trap, %g1 ! setup in case we go
1521 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1522 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1523 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1528 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1529 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step)
1531 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1532 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1536 rdpr %tstate, %g1 ! cwp for trap handler
1538 bclr TSTATE_CWP_MASK, %g1
1539 wrpr %g1, %g4, %tstate
1545 rdpr %tstate, %g1
1546 btst TSTATE_PRIV, %g1
1549 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1561 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18]
1563 smul %g1, CPTRSIZE, %g2
1572 mov 1, %g1
1573 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1574 rdpr %tpc, %g1 ! ld trapping instruction using
1575 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault
1579 andcc %g1, %g4, %g4 ! and instruction with mask
1580 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1587 set trap, %g1
1597 set trap, %g1 ! setup in case we go
1608 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1609 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1610 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1615 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1616 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step)
1618 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1619 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1626 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1632 ldn [%g1 + T_LWP], %g1 ! load klwp pointer
1633 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1637 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb
1651 CPU_ADDR(%g1, %g4)
1652 stx %fsr, [%g1 + CPU_TMP1]
1653 ldx [%g1 + CPU_TMP1], %g2
1696 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
1723 std %d62, [%g1 + CPU_TMP1] ! save original value
1814 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62
1852 set _fp_exception, %g1
1862 rdpr %tnpc, %g1
1863 wrpr %g1, %tpc
1864 add %g1, 4, %g1
1865 wrpr %g1, %tnpc
1866 set trap, %g1
1898 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
1899 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1900 ldn [%g1 + T_PROCP], %g1
1902 stb %g2, [%g1 + P_FIXALIGNMENT]
2056 CPU_ADDR(%g1, %g4)
2058 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2124 CPU_ADDR(%g1, %g4)
2126 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2178 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2180 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2181 set trap_freeze, %g1
2183 st %g2, [%g1]
2187 set trap_freeze, %g1
2188 st %g0, [%g1]
2189 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2191 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2197 CPU_ADDR(%g1, %g2)
2198 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2205 mov %o0, %g1 ! move ccr to normal %g1
2208 CPU_ADDR(%g1, %g2)
2209 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2213 CPU_ADDR(%g1, %g2)
2214 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2216 mov %g1, %o0
2219 CPU_ADDR(%g1, %g2)
2228 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2241 rdpr %tstate, %g1 ! get tstate
2242 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr
2246 rd %fprs, %g1 ! get fprs
2247 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2263 rdpr %tstate, %g1 ! get tstate
2268 andn %g1, %g2, %g1 ! zero current user bits
2272 wrpr %g1, %g3, %tstate ! write tstate
2279 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2280 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2296 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2297 ld [%g1 + CPU_ID], %o0 ! load cpu_id
2298 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2300 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2301 sra %g1, 0, %o1
2309 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2310 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2314 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals
2315 st %l1, [%g1 + CPU_TMP2]
2319 mov %g1, %l0 ! save CPU struct addr
2331 mov %g1, %l0 ! save CPU struct addr
2333 cmp %g1, OSYS_mmap ! compare to old 4.x mmap
2334 movz %icc, SYS_mmap, %g1
2346 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2347 st %l0, [%g1 + CPU_TMP1] ! save some locals
2348 st %l1, [%g1 + CPU_TMP2]
2349 mov %g1, %l0 ! preserve CPU addr
2351 mov %g1, %l1
2430 mov PTL1_BAD_MMUTRAP, %g1
2434 mov PTL1_BAD_MMUTRAP, %g1
2442 mov PTL1_BAD_MMUTRAP, %g1
2477 jmp %g1 + 0
2484 jmp %g1 + 0
2621 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer
2655 TRACE_PTR(%g1, %g6)
2657 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi
2659 stna %g6, [%g1 + TRAP_ENT_TPC]%asi
2661 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi
2662 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
2663 stna %g0, [%g1 + TRAP_ENT_F1]%asi
2664 stna %g0, [%g1 + TRAP_ENT_F2]%asi
2665 stna %g0, [%g1 + TRAP_ENT_F3]%asi
2666 stna %g0, [%g1 + TRAP_ENT_F4]%asi
2667 TRACE_SAVE_TL_GL_REGS(%g1, %g6)
2669 stha %g6, [%g1 + TRAP_ENT_TT]%asi
2677 stxa %g6, [%g1 + TRAP_ENT_TR]%asi ! context ID
2678 TRACE_NEXT(%g1, %g4, %g5)
2706 mov MMFSA_F_UNALIGN, %g1
2711 or %g3, %g1, %g3 /* SFSR */
2723 mov MMFSA_F_UNALIGN, %g1
2728 or %g3, %g1, %g3 /* SFSR */
2736 ldx [%g3 + MMFSA_D_TYPE], %g1
2741 or %g3, %g1, %g3 /* SFSR */
2746 mov T_DATA_EXCEPTION, %g1
2825 set fast_trap_dummy_call, %g1
2844 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
2863 mov %pc, %g1 ;\
2864 add %g1, 16, %g1 ;\