Lines Matching refs:uint32_t
41 uint32_t pad[3];
48 uint32_t devid; /* 0x0.0000 All, device ID */
50 uint32_t devtemp; /* 0x0.0010 All */
52 uint32_t incon_scratch; /* 0x0.0020 All */
54 uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */
56 uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */
58 uint32_t device_conf; /* 0x0.0050 All, device configuration */
60 uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */
62 uint32_t device_rststat; /* 0x0.0070 All, device reset status */
64 uint32_t device_errstat; /* 0x0.0080 SBBC, device reset */
66 uint32_t device_errcntl; /* 0x0.0090 SBBC,device error control */
68 uint32_t jtag_cntl; /* 0x0.00a0 SBBC and SDC,JTAG control */
70 uint32_t jtag_cmd; /* 0x0.00b0 SBBC and SDC,JTAG command */
72 uint32_t i2c_addrcmd; /* 0x0.00c0 SBBC,I2C addr and command */
74 uint32_t i2c_data; /* 0x0.00d0 SBBC, I2C data */
76 uint32_t pci_errstat; /* 0x0.00e0 SBBC, PCI error status */
78 uint32_t consbus_conf; /* 0x0.0300 All */
80 uint32_t consbus_erraddr; /* 0x0.0310 SBBC */
82 uint32_t consbus_errack; /* 0x0.0320 SBBC */
84 uint32_t pad5;
85 uint32_t consbus_port0_err; /* 0x0.0400 All */
87 uint32_t pad7[2];
88 uint32_t consbus_part_dom_err; /* 0x0.04f0 SBBC and CBH */
90 uint32_t pad8a[2];
91 uint32_t sbbc_synch; /* 0x0.1000 SBBC */
93 uint32_t padqa[3];
94 uint32_t dev_access_tim0; /* 0x0.1100 SBBC */
96 uint32_t dev_access_tim1; /* 0x0.1110 SBBC */
98 uint32_t dev_access_tim2; /* 0x0.1120 SBBC */
100 uint32_t dev_access_tim3; /* 0x0.1130 SBBC */
102 uint32_t dev_access_tim4; /* 0x0.1140 SBBC */
104 uint32_t dev_access_tim5; /* 0x0.1150 SBBC */
106 uint32_t pad9a[1];
107 uint32_t spare_in_out; /* 0x0.1200 SBBC */
109 uint32_t pad10a[2];
110 uint32_t monitor_cntl; /* 0x0.1800 SBBC */
112 uint32_t pad11a[1];
113 uint32_t port_intr_gen0; /* 0x0.2000 SBBC */
115 uint32_t port_intr_gen1; /* 0x0.2010 SBBC */
117 uint32_t syscntlr_intr_gen; /* 0x0.2020 SBBC */
119 uint32_t sys_intr_status; /* 0x0.2300 SBBC */
121 uint32_t sys_intr_enable; /* 0x0.2310 SBBC */
123 uint32_t pci_intr_status; /* 0x0.2320 SBBC */
125 uint32_t pci_intr_enable; /* 0x0.2330 SBBC */
127 uint32_t pad13a[1];
128 uint32_t pci_to_consbus_map; /* 0x0.4000 SBBC */
130 uint32_t consbus_to_pci_map; /* 0x0.4010 SBBC */
131 uint32_t pad14[2247];
226 uint32_t devid; /* All, device ID */
227 uint32_t devtemp; /* All */
228 uint32_t incon_scratch; /* All */
229 uint32_t incon_tstl1; /* AR and SDC */
230 uint32_t incon_tsterr; /* AR and SDC */
231 uint32_t device_conf; /* All, device configuration */
232 uint32_t device_rstcntl; /* SBBC and AR, dev reset control */
233 uint32_t device_rststat; /* All, device reset status */
234 uint32_t device_errstat; /* SBBC, device reset */
235 uint32_t device_errcntl; /* SBBC, device error control */
236 uint32_t jtag_cntl; /* SBBC and SDC, JTAG control */
237 uint32_t jtag_cmd; /* SBBC and SDC, JTAG command */
238 uint32_t i2c_addrcmd; /* SBBC, I2C address and command */
239 uint32_t i2c_data; /* SBBC, I2C data */
240 uint32_t pci_errstat; /* SBBC, PCI error status */
241 uint32_t domain_conf; /* CBH */
242 uint32_t safari_port0_conf; /* AR and SDC */
243 uint32_t safari_port1_conf; /* AR and SDC */
244 uint32_t safari_port2_conf; /* AR and SDC */
245 uint32_t safari_port3_conf; /* AR and SDC */
246 uint32_t safari_port4_conf; /* AR and SDC */
247 uint32_t safari_port5_conf; /* AR and SDC */
248 uint32_t safari_port6_conf; /* AR and SDC */
249 uint32_t safari_port7_conf; /* AR and SDC */
250 uint32_t safari_port8_conf; /* AR and SDC */
251 uint32_t safari_port9_conf; /* AR and SDC */
252 uint32_t safari_port0_err; /* AR and SDC */
253 uint32_t safari_port1_err; /* AR and SDC */
254 uint32_t safari_port2_err; /* AR and SDC */
255 uint32_t safari_port3_err; /* AR and SDC */
256 uint32_t safari_port4_err; /* AR and SDC */
257 uint32_t safari_port5_err; /* AR and SDC */
258 uint32_t safari_port6_err; /* AR and SDC */
259 uint32_t safari_port7_err; /* AR and SDC */
260 uint32_t safari_port8_err; /* AR and SDC */
261 uint32_t safari_port9_err; /* AR and SDC */
262 uint32_t consbus_conf; /* All */
263 uint32_t consbus_erraddr; /* SBBC */
264 uint32_t consbus_errack; /* SBBC */
265 uint32_t consbus_errinj0; /* CBH */
266 uint32_t consbus_errinj1; /* CBH */
267 uint32_t consbus_port0_err; /* All */
268 uint32_t consbus_port1_err; /* SDC and CBH */
269 uint32_t consbus_port2_err; /* SDC and CBH */
270 uint32_t consbus_port3_err; /* SDC and CBH */
271 uint32_t consbus_port4_err; /* SDC and CBH */
272 uint32_t consbus_port5_err; /* CBH */
273 uint32_t consbus_port6_err; /* CBH */
274 uint32_t consbus_port7_err; /* CBH */
275 uint32_t consbus_port8_err; /* CBH */
276 uint32_t consbus_port9_err; /* CBH */
277 uint32_t consbus_porta_err; /* CBH */
278 uint32_t consbus_portb_err; /* CBH */
279 uint32_t consbus_portc_err; /* CBH */
280 uint32_t consbus_portd_err; /* CBH */
281 uint32_t consbus_porte_err; /* CBH */
282 uint32_t consbus_part_dom_err; /* SBBC and CBH */
283 uint32_t sbbc_synch; /* SBBC */
284 uint32_t dev_access_tim0; /* SBBC */
285 uint32_t dev_access_tim1; /* SBBC */
286 uint32_t dev_access_tim2; /* SBBC */
287 uint32_t dev_access_tim3; /* SBBC */
288 uint32_t dev_access_tim4; /* SBBC */
289 uint32_t dev_access_tim5; /* SBBC */
290 uint32_t spare_in_out; /* SBBC */
291 uint32_t monitor_cntl; /* SBBC */
292 uint32_t port_intr_gen0; /* SBBC */
293 uint32_t port_intr_gen1; /* SBBC */
294 uint32_t syscntlr_intr_gen; /* SBBC */
295 uint32_t sys_intr_status; /* SBBC */
296 uint32_t sys_intr_enable; /* SBBC */
297 uint32_t pci_intr_status; /* SBBC */
298 uint32_t pci_intr_enable; /* SBBC */
299 uint32_t pci_to_consbus_map; /* SBBC */
300 uint32_t consbus_to_pci_map; /* SBBC */
301 uint32_t scm_consbus_addrmap; /* CBH */
302 uint32_t ar_slot0_trans_cnt; /* AR */
303 uint32_t ar_slot1_trans_cnt; /* AR */
304 uint32_t ar_slot2_trans_cnt; /* AR */
305 uint32_t ar_slot3_trans_cnt; /* AR */
306 uint32_t ar_slot4_trans_cnt; /* AR */
307 uint32_t ar_slot5_trans_cnt; /* AR */
308 uint32_t ar_slot6_trans_cnt; /* AR */
309 uint32_t ar_slot7_trans_cnt; /* AR */
310 uint32_t ar_slot8_trans_cnt; /* AR */
311 uint32_t ar_slot9_trans_cnt; /* AR */
312 uint32_t ar_trans_cnt_oflow; /* AR */
313 uint32_t ar_trans_cnt_uflow; /* AR */
314 uint32_t ar_l1l1_conf; /* AR */
315 uint32_t lock_step_err; /* AR and SDC */
316 uint32_t l2_check_err; /* AR and SDC */
317 uint32_t incon_tstl1_slave; /* AR */
318 uint32_t incon_tstl2_slave; /* AR and SDC */
319 uint32_t ecc_status; /* SDC */
320 uint32_t event_counter0; /* SDC */
321 uint32_t event_counter1; /* SDC */
322 uint32_t event_counter2; /* SDC */
323 uint32_t monitor_counter_cntl; /* AR and SDC */
324 uint32_t ar_transid_match; /* AR */