Lines Matching defs:sbbc_regs_map
47 struct sbbc_regs_map { struct
48 uint32_t devid; /* 0x0.0000 All, device ID */
49 pad12_t pada;
50 uint32_t devtemp; /* 0x0.0010 All */
51 pad12_t padb;
52 uint32_t incon_scratch; /* 0x0.0020 All */
53 pad12_t padc;
54 uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */
55 pad12_t padd;
56 uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */
57 pad12_t pade;
58 uint32_t device_conf; /* 0x0.0050 All, device configuration */
59 pad12_t padf;
60 uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */
61 pad12_t padg;
62 uint32_t device_rststat; /* 0x0.0070 All, device reset status */
63 pad12_t padh;
64 uint32_t device_errstat; /* 0x0.0080 SBBC, device reset */
65 pad12_t padi;
66 uint32_t device_errcntl; /* 0x0.0090 SBBC,device error control */
67 pad12_t padj;
68 uint32_t jtag_cntl; /* 0x0.00a0 SBBC and SDC,JTAG control */
69 pad12_t padk;
70 uint32_t jtag_cmd; /* 0x0.00b0 SBBC and SDC,JTAG command */
71 pad12_t padl;
72 uint32_t i2c_addrcmd; /* 0x0.00c0 SBBC,I2C addr and command */
73 pad12_t padm;
74 uint32_t i2c_data; /* 0x0.00d0 SBBC, I2C data */
75 pad12_t padn;
76 uint32_t pci_errstat; /* 0x0.00e0 SBBC, PCI error status */
77 pad12_t pad2[45];
78 uint32_t consbus_conf; /* 0x0.0300 All */
79 pad12_t pado;
80 uint32_t consbus_erraddr; /* 0x0.0310 SBBC */
81 pad12_t padp;
82 uint32_t consbus_errack; /* 0x0.0320 SBBC */
83 pad12_t pad4[18];
84 uint32_t pad5;
85 uint32_t consbus_port0_err; /* 0x0.0400 All */
86 pad12_t pad6[19];
87 uint32_t pad7[2];
88 uint32_t consbus_part_dom_err; /* 0x0.04f0 SBBC and CBH */
89 pad12_t pad8[235];
90 uint32_t pad8a[2];
91 uint32_t sbbc_synch; /* 0x0.1000 SBBC */
92 pad12_t padq[20];
93 uint32_t padqa[3];
94 uint32_t dev_access_tim0; /* 0x0.1100 SBBC */
95 pad12_t padr;
96 uint32_t dev_access_tim1; /* 0x0.1110 SBBC */
97 pad12_t pads;
98 uint32_t dev_access_tim2; /* 0x0.1120 SBBC */
99 pad12_t padt;
100 uint32_t dev_access_tim3; /* 0x0.1130 SBBC */
101 pad12_t padu;
102 uint32_t dev_access_tim4; /* 0x0.1140 SBBC */
103 pad12_t padv;
104 uint32_t dev_access_tim5; /* 0x0.1150 SBBC */
105 pad12_t pad9[14];
106 uint32_t pad9a[1];
107 uint32_t spare_in_out; /* 0x0.1200 SBBC */
108 pad12_t pad10[127];
109 uint32_t pad10a[2];
110 uint32_t monitor_cntl; /* 0x0.1800 SBBC */
111 pad12_t pad11[170];
112 uint32_t pad11a[1];
113 uint32_t port_intr_gen0; /* 0x0.2000 SBBC */
114 pad12_t padw;
115 uint32_t port_intr_gen1; /* 0x0.2010 SBBC */
116 pad12_t padx;
117 uint32_t syscntlr_intr_gen; /* 0x0.2020 SBBC */
118 pad12_t pad12[61];
119 uint32_t sys_intr_status; /* 0x0.2300 SBBC */
120 pad12_t pady;
121 uint32_t sys_intr_enable; /* 0x0.2310 SBBC */
122 pad12_t padz;
123 uint32_t pci_intr_status; /* 0x0.2320 SBBC */
124 pad12_t padaa;
125 uint32_t pci_intr_enable; /* 0x0.2330 SBBC */
126 pad12_t pad13[614];
127 uint32_t pad13a[1];
128 uint32_t pci_to_consbus_map; /* 0x0.4000 SBBC */
129 pad12_t padab;
130 uint32_t consbus_to_pci_map; /* 0x0.4010 SBBC */
131 uint32_t pad14[2247];