Lines Matching +full:prefetch +full:- +full:dma
40 * Schizo-specific register offsets & bit field positions.
45 * 0x00 <chip_type> <version#> <module-revision#>
162 * MAX_PRF when enabled will always prefetch the max of 8
189 * Schizo-specific fields of interrupt mapping register:
331 #define SCHIZO_VPN_MASK ((1 << 19) - 1)
379 * XMITS PCI-X Diagnostic Register bit definitions
393 * XMITS PCI-X Error Status Register bit definitions
403 * As a workaround for an XMITS ASIC bug, the following PCI-X errors are
404 * assigned new bit positions within the PCI-X Error Status Register to
409 * -------------------- ------------ ------------
426 * PCI-X Message Classes and Indexes
458 #define PCIX_ERRREG_OFFSET (XMITS_PCI_X_ERROR_STATUS_REG_OFFSET -\
462 * Nested message structure to allow for storing all the PCI-X
523 #define TLBDATA_MEMPA_BITS ((0x1ull << 30) - 1)
528 * pbm_cdma_flag(schizo only): consistent dma sync handshake
545 (((cmn_p->pci_chip_id >> 16) == PCI_CHIP_SCHIZO) ? PCI_SCHIZO : \
546 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_TOMATILLO) ? PCI_TOMATILLO : \
547 ((cmn_p->pci_chip_id >> 16) == PCI_CHIP_XMITS) ? PCI_XMITS : "")
551 #define NBIGN(ib_p) ((ib_p)->ib_ign ^ 1)
565 * The following macro defines the 42-bit bus width support for SAFARI bus