Lines Matching +full:clock +full:- +full:frequency

89  * OBP supplies us with 3 register sets for the clock-board node. The code for
96  * 	0	Clock frequency registers
98  *	2       Clock version register
107 #define	SYS_OFF_CLK_FREQ2	0x2	/* offset of clock register 2 */
109 /* Important bits for Clock Frequency register 2 */
113 #define	CLOCK_FREQ_8	0x01	/* Frequency bit 8 */
115 #define	CLOCK_RANGE	0x0c	/* Bits 3:2 control the clock range */
129 /* Register set 2 (not present on old vintage clock boards) */
130 #define	CLK_VERSION_REG	0x0	/* Offset of clock version register */
157 #define	SYS_GEN_NOT_RST		0x01	/* ==0 if clock freq reset occured */
166 /* Bit field defines for Clock Version Register */
170 /* Macros to determine frequency capability from clock version register */
185 #define	SYS_CLK_33_OK		0x20	/* 3.3V OK on clock board */
186 #define	SYS_CLK_50_OK		0x10	/* 5.0V OK on clock board */
230  * several power supplies are managed -- 8 core power supplies,
231  * up to two pps, a couple of clock board powers and a register worth
262  * B	- bottom 4 bits (16 slots) are for the slot/receptacle id
263  * I	- next 4 bits are for the instance number
264  * X	- rest are not used
278 #define	HOTPLUG_DISABLED_PROPERTY "hotplug-disabled"
370 	uchar_t nslots;			/* slots in this system (0-16) */
372 	pnode_t options_nodeid;		/* for nvram powerfail-time */
375 	ddi_idevice_cookie_t idevice;	/* TODO - Do we need this? */
381 	ddi_softintr_t ac_fail_high_id;	/* ac fail re-enable softintr id */
386 	ddi_softintr_t pps_fan_high_id;	/* pps fan re-enable softintr id */
392 	volatile uchar_t *clk_freq1;	/* Clock frequency reg. 1 */
393 	volatile uchar_t *clk_freq2;	/* Clock frequency reg. 2 */
401 	volatile uchar_t *clk_ver;	/* clock version register */
444 	struct kstat_named	clk_freq2;	/* Clock register 2 */
448 	struct kstat_named	clk_ver;	/* clock version register */
451 #define	SYSC_ERR_SET(pkt, err)	(pkt)->cmd_cfga.errtype = (err)