Lines Matching +full:board +full:- +full:2

56  *	2	FanFail IMR, ISMR
71 #define FHC_OFF_BSR 0x30 /* FHC Board Status Register */
75 /* Register sets 2-5, the ISMR offset is the same */
104 /* Macros for decoding UPA speed pins from the Board Status Register */
112 /* Macro for extracting the "plus" bit from the Board Status Register */
123 #define FHC_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
125 #define FHC_JTAG_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
127 #define FHC_IGN(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
129 #define FHC_SIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
131 #define FHC_SSM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
133 #define FHC_UIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
135 #define FHC_USM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ argument
139 * the foolowing defines are used for trans phy-addr to board number
149 * later by JTAG scan to determine board type.
157 /* Bit field defines for Board Status Register */
160 /* Bit field defines for the FHC Board Status Register when on a disk board */
170 /* Maximum number of Board Power Supplies. */
184 * Most Sunfire ASICs have the chip rev encoded into bits 31-28 of the
208 * Convert the Board Number field in the FHC Board Status Register to
209 * a board number. The field in the register is bits 0,3-1 of the board
210 * number. Therefore a macro is necessary to extract the board number.
219 #define FHC_BOARD2CPU_A(board) ((board) << 1) argument
220 #define FHC_BOARD2CPU_B(board) (((board) << 1) + 1) argument
222 #define FHC_BOARD2PS(board) ((((board) & 0xc) >> 1) | ((board) & 0x1)) argument
240 * Each Sunfire CPU Board has 32Kbytes of SRAM on the FireHose Bus.
244 * 0x1ff.f020.0000 - 0x1ff.f020.5fff scratch/stacks
245 * 0x1ff.f020.6000 - 0x1ff.f020.67ff reset info (2K bytes)
246 * 0x1ff.f020.6800 - 0x1ff.f020.6fff POST private (2K bytes)
247 * 0x1ff.f020.7000 - 0x1ff.f020.77ff OS private (2K bytes)
248 * 0x1ff.f020.7800 - 0x1ff.f020.7fff OBP private (2K bytes)
273 * will be in degrees Centigrade, corrected for the board type the
274 * temperature was read from. Since each Board type has a different
304 #define OVERTEMP_TIMEOUT_SEC 2
306 /* definition of the clock board index */
310 #define L2_SZ 15 /* size of array for level 2 samples */
313 #define L5_SZ 2 /* size of array for level 5 samples */
335 * State variable for board temperature. Each board has its own
336 * temperature state. State transitions from OK -> bad direction
341 enum temp_state { TEMP_OK = 0, /* normal board temperature */
343 TEMP_DANGER = 2 }; /* get ready to shutdown */
367 TREND_FALL = 2, /* Falling temperature */
374 #define NOISE_THRESH 2
387 short l2[L2_SZ]; /* level 2 samples */
393 enum temp_state state; /* state of board temperature */
397 enum temp_trend trend; /* temperature trend for board */
464 enum ft_class fclass; /* System or board class fault */
481 * Board list management.
487 EMPTY_BOARD = -1,
488 UNINIT_BOARD = 0, /* Uninitialized board type */
489 UNKNOWN_BOARD, /* Unknown board type */
490 CPU_BOARD, /* System board CPU(s) */
491 MEM_BOARD, /* System board no CPUs */
492 IO_2SBUS_BOARD, /* 2 SBus & SOC IO Board */
493 IO_SBUS_FFB_BOARD, /* SBus & FFB SOC IO Board */
494 IO_PCI_BOARD, /* PCI IO Board */
495 DISK_BOARD, /* Disk Drive Board */
496 CLOCK_BOARD, /* System Clock board */
497 IO_2SBUS_SOCPLUS_BOARD, /* 2 SBus & SOC+ IO board */
498 IO_SBUS_FFB_SOCPLUS_BOARD /* SBus&FFB&SOC+ board */
502 * Defined strings for comparing with OBP board-type property. If OBP ever
503 * changes the board-type properties, these string defines must be changed
508 #define IO_2SBUS_BD_NAME "dual-sbus"
509 #define IO_SBUS_FFB_BD_NAME "upa-sbus"
510 #define IO_PCI_BD_NAME "dual-pci"
512 #define IO_2SBUS_SOCPLUS_BD_NAME "dual-sbus-soc+"
513 #define IO_SBUS_FFB_SOCPLUS_BD_NAME "upa-sbus-soc+"
518 * XXX - We cannot determine Spitfire rev from JTAG scan, so it is
548 #define FFB_FAILED -1
551 #define FFB_DOUBLE 2
576 int disk_pres[2];
577 int disk_id[2];
581 struct cpu_info cpu[2];
596 UNKNOWN_STATE = 0, /* Unknown board */
598 HOTPLUG_STATE, /* Hot plugged board */
599 LOWPOWER_STATE, /* Powered down board */
600 DISABLED_STATE, /* Board disabled by PROM */
601 FAILED_STATE /* Board failed by POST */
605 enum board_type type; /* Type of board */
606 enum board_state state; /* current state of this board */
607 int board; /* board number */ member
677 sysc_cfga_cond_t condition; /* current board condition */
679 uint_t in_transition:1; /* board is in_transition */
682 enum board_type type; /* Type of board */
683 int board; /* board number */ member
688 uint_t no_detach:1; /* board is non_detachable */
689 uint_t plus_board:1; /* board is 98 MHz capable */
720 dev_info_t **dip_list; /* list of top dips for board */
780 * The board list structure is the central storage for the kernel's
785 sysc_cfga_stat_t sc; /* board info */
786 sysc_dr_handle_t sh[2]; /* sysctrl dr interface */
790 int fault; /* failure on this board? */
791 int flags; /* board state flags */
795 * Fhc_bd.c holds 2 resizable arrays of boards. First for clock
806 #define BDF_VALID 0x1 /* board entry valid */
807 #define BDF_DETACH 0x2 /* board detachable */
808 #define BDF_DISABLED 0x4 /* board disabled */
813 * Board list management interface.
848 * oven, the test people will set the 'mfg-mode' property in the
858 #define MAX_ZS_CNT 2
874 * the JTAG controller on this system board. The controller can only
893 int board; /* reference our board element */ member
901 void fhc_add_memloc(int board, uint64_t pa, uint_t size);
902 void fhc_del_memloc(int board);
904 void fhc_program_memory(int board, uint64_t base);
909 struct bd_list *list; /* pointer to board list entry */
913 volatile uint_t *bsr; /* FHC Board Status register */
941 enum board_type get_board_type(int board);
951 extern int fhc_board_poweroffcpus(int board, char *errbuf, int cpu_flags);
965 struct kstat_named bsr; /* FHC Board Status Register */