Lines Matching refs:g4
124 sub %g0, 1, %g4 ;\
154 sub %g0, 1, %g4 ;\
173 sub %g0, 1, %g4 ;\
195 sub %g0, 1, %g4 ;\
235 sub %g0, 1, %g4 ;\
246 sub %g0, 1, %g4 ;\
253 sub %g0, 1, %g4 ;\
337 add %sp, 16, %g4 ;\
338 sta %l4, [%g4 + %g0]asi_num ;\
339 sta %l5, [%g4 + %g1]asi_num ;\
340 sta %l6, [%g4 + %g2]asi_num ;\
341 sta %l7, [%g4 + %g3]asi_num ;\
342 add %g4, 16, %g4 ;\
343 sta %i0, [%g4 + %g0]asi_num ;\
344 sta %i1, [%g4 + %g1]asi_num ;\
345 sta %i2, [%g4 + %g2]asi_num ;\
346 sta %i3, [%g4 + %g3]asi_num ;\
347 add %g4, 16, %g4 ;\
348 sta %i4, [%g4 + %g0]asi_num ;\
349 sta %i5, [%g4 + %g1]asi_num ;\
350 sta %i6, [%g4 + %g2]asi_num ;\
351 sta %i7, [%g4 + %g3]asi_num ;\
442 add %sp, 16, %g4 ;\
443 lda [%g4 + %g0]asi_num, %l4 ;\
444 lda [%g4 + %g1]asi_num, %l5 ;\
445 lda [%g4 + %g2]asi_num, %l6 ;\
446 lda [%g4 + %g3]asi_num, %l7 ;\
447 add %g4, 16, %g4 ;\
448 lda [%g4 + %g0]asi_num, %i0 ;\
449 lda [%g4 + %g1]asi_num, %i1 ;\
450 lda [%g4 + %g2]asi_num, %i2 ;\
451 lda [%g4 + %g3]asi_num, %i3 ;\
452 add %g4, 16, %g4 ;\
453 lda [%g4 + %g0]asi_num, %i4 ;\
454 lda [%g4 + %g1]asi_num, %i5 ;\
455 lda [%g4 + %g2]asi_num, %i6 ;\
456 lda [%g4 + %g3]asi_num, %i7 ;\
540 mov 24 + V9BIAS64, %g4 ;\
541 stxa %l3, [%sp + %g4]asi_num ;\
546 stxa %l7, [%g5 + %g4]asi_num ;\
551 stxa %i3, [%g5 + %g4]asi_num ;\
556 stxa %i7, [%g5 + %g4]asi_num ;\
640 mov V9BIAS64 + 24, %g4 ;\
641 ldxa [%sp + %g4]asi_num, %l3 ;\
646 ldxa [%g5 + %g4]asi_num, %l7 ;\
651 ldxa [%g5 + %g4]asi_num, %i3 ;\
656 ldxa [%g5 + %g4]asi_num, %i7 ;\
760 add %sp, 16, %g4 ;\
761 sta %l4, [%g4 + %g0]asi_num ;\
762 sta %l5, [%g4 + %g1]asi_num ;\
763 sta %l6, [%g4 + %g2]asi_num ;\
764 sta %l7, [%g4 + %g3]asi_num ;\
765 add %g4, 16, %g4 ;\
766 sta %i0, [%g4 + %g0]asi_num ;\
767 sta %i1, [%g4 + %g1]asi_num ;\
768 sta %i2, [%g4 + %g2]asi_num ;\
769 sta %i3, [%g4 + %g3]asi_num ;\
770 add %g4, 16, %g4 ;\
771 sta %i4, [%g4 + %g0]asi_num ;\
772 sta %i5, [%g4 + %g1]asi_num ;\
773 sta %i6, [%g4 + %g2]asi_num ;\
774 sta %i7, [%g4 + %g3]asi_num ;\
789 mov 24 + V9BIAS64, %g4 ;\
790 stxa %l3, [%sp + %g4]asi_num ;\
795 stxa %l7, [%g5 + %g4]asi_num ;\
800 stxa %i3, [%g5 + %g4]asi_num ;\
805 stxa %i7, [%g5 + %g4]asi_num ;\
871 sethi %hi(.check_v9utrap), %g4 ;\
872 jmp %g4 + %lo(.check_v9utrap) ;\
883 sethi %hi(.check_v9utrap), %g4 ;\
884 jmp %g4 + %lo(.check_v9utrap) ;\
895 sethi %hi(.check_v9utrap), %g4 ;\
896 jmp %g4 + %lo(.check_v9utrap) ;\
906 sethi %hi(.check_v9utrap), %g4 ;\
907 jmp %g4 + %lo(.check_v9utrap) ;\
920 mov level, %g4 ;\
925 mov PIL_14, %g4 ;\
930 mov PIL_15, %g4 ;\
1020 sethi %hi(TAGACC_CTX_MASK), %g4 ;\
1021 or %g4, %lo(TAGACC_CTX_MASK), %g4 ;\
1022 and %g2, %g4, %g3 /* g3 = ctx */ ;\
1024 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1027 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1030 and %g6, %g4, %g6 /* &= CTXREG_CTX_MASK */ ;\
1072 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\
1073 cmp %g4, %g7 ;\
1109 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\
1110 cmp %g4, %g7 ;\
1163 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\
1164 cmp %g4, %g7 ;\
1202 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\
1203 cmp %g4, %g7 ;\
1283 GET_TRACE_TICK(%g6, %g4) ;\
1299 ldxa [%g0]ASI_DMMU, %g4 ;\
1301 movne %icc, %g4, %g1 ;\
1304 TRACE_NEXT(%g3, %g4, %g6)
1583 mov MMU_TAG_ACCESS, %g4
1584 ldxa [%g4]ASI_IMMU, %g2 ! arg1 = addr
1588 mov -1, %g4
1595 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1621 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1634 CPU_INDEX(%g4, %g5)
1636 sllx %g4, CPU_CORE_SHIFT, %g4
1637 add %g4, %g5, %g4
1638 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5
1642 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS]
1649 mov 1, %g4 ! running on Panther CPUs
1650 sllx %g4, PN_SFSR_PARITY_SHIFT, %g4 ! since US-I/II use the same
1651 andcc %g3, %g4, %g0 ! bit for something else which
1657 set itlb_parity_trap, %g4
1661 set dtlb_parity_trap, %g4
1670 sub %g0, 1, %g4
1672 jmp %g4 ! off to the appropriate
1676 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1682 rdpr %tstate, %g4
1683 btst TSTATE_PRIV, %g4
1709 sub %g0, 1, %g4
1716 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1730 sub %g0, 1, %g4
1740 sub %g0, 1, %g4 ! the save instruction below
1749 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1765 rdpr %cwp, %g4
1767 wrpr %g1, %g4, %tstate
1777 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1778 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer
1801 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1804 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR
1806 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction
1807 andcc %g1, %g4, %g4 ! and instruction with mask
1808 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1817 sub %g0, 1, %g4
1827 sub %g0, 1, %g4 ! the save instruction below
1836 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1850 rdpr %cwp, %g4
1852 wrpr %g2, %g4, %tstate
1854 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1855 ldn [%g4 + P_AS], %g4 ! load as pointer
1856 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit
1857 cmp %l7, %g4 ! check for single-step set
1861 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1862 cmp %g4, STEP_ACTIVE ! step flags set in pcb?
1866 mov %l7, %g4 ! on entry to precise user trap
1869 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS,
1870 ! %g4 == userlimit
1879 CPU_ADDR(%g1, %g4)
1955 set _fitos_fitod_table, %g4
1957 jmp %g4 + %g7
2001 set _fitos_fdtos_table, %g4
2003 jmp %g4 + %g7
2082 sub %g0, 1, %g4
2089 sub %g0, 1, %g4
2095 CPU_ADDR(%g4, %g5)
2096 ldn [%g4 + CPU_MPCB], %g4
2097 brz,a,pn %g4, 1f
2099 ld [%g4 + MPCB_WSTATE], %g5
2292 CPU_ADDR(%g1, %g4)
2293 or %g0, 1, %g4
2294 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2348 sub %g0, 1, %g4
2362 CPU_ADDR(%g1, %g4)
2363 or %g0, 1, %g4
2364 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2411 sub %g0, 1, %g4
2416 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2418 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2427 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2429 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2516 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2517 wr %g0, %g4, %fprs ! write fprs
2523 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2524 srlx %g4, 2, %g4 ! shift fef value to bit 0
2525 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2772 set CTXREG_CTX_MASK, %g4 ! check Pcontext
2773 btst %g4, %g1
2801 GET_TRACE_TICK(%g6, %g4)
2812 TRACE_NEXT(%g3, %g4, %g5)
2857 stxa %g4, [%g5 + TRAP_ENT_F1]%asi ! tsb tag
2858 GET_TRACE_TICK(%g6, %g4)
2870 or %g6, TT_MMU_MISS, %g4
2871 stha %g4, [%g5 + TRAP_ENT_TT]%asi
2878 TRACE_NEXT(%g5, %g4, %g6)
2907 TRACE_NEXT(%g1, %g4, %g5)
2996 mov -1, %g4