Lines Matching refs:g1
121 set trap, %g1 ;\
151 set trap, %g1 ;\
171 set (which), %g1 ;\
193 set trap, %g1 ;\
229 rdpr %tstate, %g1 ;\
230 btst TSTATE_PRIV, %g1 ;\
233 set trap, %g1 ;\
244 set dtrace_pid_probe, %g1 ;\
251 set dtrace_return_probe, %g1 ;\
331 mov 4, %g1 ;\
332 sta %l1, [%sp + %g1]asi_num ;\
339 sta %l5, [%g4 + %g1]asi_num ;\
344 sta %i1, [%g4 + %g1]asi_num ;\
349 sta %i5, [%g4 + %g1]asi_num ;\
435 mov 4, %g1 ;\
438 lda [%sp + %g1]asi_num, %l1 ;\
444 lda [%g4 + %g1]asi_num, %l5 ;\
449 lda [%g4 + %g1]asi_num, %i1 ;\
454 lda [%g4 + %g1]asi_num, %i5 ;\
534 mov 0 + V9BIAS64, %g1 ;\
535 2: stxa %l0, [%sp + %g1]asi_num ;\
543 stxa %l4, [%g5 + %g1]asi_num ;\
548 stxa %i0, [%g5 + %g1]asi_num ;\
553 stxa %i4, [%g5 + %g1]asi_num ;\
633 mov V9BIAS64 + 0, %g1 ;\
635 ldxa [%sp + %g1]asi_num, %l0 ;\
643 ldxa [%g5 + %g1]asi_num, %l4 ;\
648 ldxa [%g5 + %g1]asi_num, %i0 ;\
653 ldxa [%g5 + %g1]asi_num, %i4 ;\
754 mov 4, %g1 ;\
755 sta %l1, [%sp + %g1]asi_num ;\
762 sta %l5, [%g4 + %g1]asi_num ;\
767 sta %i1, [%g4 + %g1]asi_num ;\
772 sta %i5, [%g4 + %g1]asi_num ;\
783 mov 0 + V9BIAS64, %g1 ;\
784 stxa %l0, [%sp + %g1]asi_num ;\
792 stxa %l4, [%g5 + %g1]asi_num ;\
797 stxa %i0, [%g5 + %g1]asi_num ;\
802 stxa %i4, [%g5 + %g1]asi_num ;\
934 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g1 ;\
935 btst IRSR_BUSY, %g1 ;\
956 mov T_INSTR_EXCEPTION, %g1 ;\
965 mov T_DATA_EXCEPTION, %g1 ;\
1017 mov MMU_TAG_ACCESS, %g1 ;\
1019 ldxa [%g1]ASI_DMMU, %g2 ;\
1027 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1033 or %g1, DEMAP_SECOND, %g1 ;\
1034 or %g1, DEMAP_NUCLEUS, %g1 ;\
1035 1: stxa %g0, [%g1]ASI_DTLB_DEMAP /* MMU_DEMAP_PAGE */ ;\
1063 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1072 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, %g5 data */;\
1100 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1107 brlz,pn %g1, sfmmu_udtlb_slowpath ;\
1109 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, %g5 data */ ;\
1156 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1163 ldda [%g1]ASI_QUAD_LDD_PHYS, %g4 /* g4 = tag, g5 = data */ ;\
1193 ldxa [%g0]ASI_IMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1200 brlz,pn %g1, sfmmu_uitlb_slowpath /* if >1 TSB branch */ ;\
1202 ldda [%g1]ASI_NQUAD_LD, %g4 /* g4 = tag, g5 = data */ ;\
1244 ldxa [%g0]ASI_DMMU_TSB_8K, %g1 /* g1 = tsbe ptr */ ;\
1289 stxa %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\
1298 ldxa [%g0]ASI_IMMU, %g1 /* tag target */ ;\
1301 movne %icc, %g4, %g1 ;\
1302 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* tsb tag */ ;\
1483 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic);
1586 set trap, %g1
1591 rdpr %tstate, %g1
1592 btst TSTATE_PRIV, %g1
1595 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1596 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1597 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1598 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1614 mov T_ALIGNMENT, %g1
1617 rdpr %tstate, %g1
1618 btst TSTATE_PRIV, %g1
1621 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1622 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1623 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1624 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1631 mov T_PRIV_INSTR, %g1
1658 cmp %g1, T_INSTR_EXCEPTION ! branch to the itlb or
1662 cmp %g1, T_DATA_EXCEPTION ! to a IMMU exception
1667 or %g3, %g1, %g3
1668 set trap, %g1
1676 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1677 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1679 brz,a,pn %g1, 2f
1689 mov PTL1_BAD_FPTRAP, %g1
1691 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1692 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1707 set fp_disabled, %g1
1712 rdpr %tstate, %g1
1713 btst TSTATE_PRIV, %g1
1715 mov PTL1_BAD_FPTRAP, %g1
1716 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1717 stx %fsr, [%g1 + CPU_TMP1]
1718 ldx [%g1 + CPU_TMP1], %g2
1719 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1720 ldn [%g1 + T_PROCP], %g1 ! load proc pointer
1721 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps?
1728 set _fp_ieee_exception, %g1
1738 set trap, %g1 ! setup in case we go
1749 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1750 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1751 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1756 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1757 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step)
1759 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1760 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1764 rdpr %tstate, %g1 ! cwp for trap handler
1766 bclr TSTATE_CWP_MASK, %g1
1767 wrpr %g1, %g4, %tstate
1773 rdpr %tstate, %g1
1774 btst TSTATE_PRIV, %g1
1777 CPU_ADDR(%g4, %g1) ! load CPU struct addr
1789 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18]
1791 smul %g1, CPTRSIZE, %g2
1800 mov 1, %g1
1801 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR
1802 rdpr %tpc, %g1 ! ld trapping instruction using
1803 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault
1807 andcc %g1, %g4, %g4 ! and instruction with mask
1808 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP
1815 set trap, %g1
1825 set trap, %g1 ! setup in case we go
1836 CPU_ADDR(%g1, %g4) ! load CPU struct addr
1837 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
1838 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1843 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1844 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step)
1846 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags
1847 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1854 ldn [%g1 + T_PROCP], %g4 ! load proc pointer
1860 ldn [%g1 + T_LWP], %g1 ! load klwp pointer
1861 ld [%g1 + PCB_STEP], %g4 ! load single-step flag
1865 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb
1879 CPU_ADDR(%g1, %g4)
1880 stx %fsr, [%g1 + CPU_TMP1]
1881 ldx [%g1 + CPU_TMP1], %g2
1924 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
1951 std %d62, [%g1 + CPU_TMP1] ! save original value
2042 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62
2080 set _fp_exception, %g1
2087 set trap, %g1
2131 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2132 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer
2133 ldn [%g1 + T_PROCP], %g1
2135 stb %g2, [%g1 + P_FIXALIGNMENT]
2292 CPU_ADDR(%g1, %g4)
2294 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2362 CPU_ADDR(%g1, %g4)
2364 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag
2416 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2418 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2419 set trap_freeze, %g1
2421 st %g2, [%g1]
2425 set trap_freeze, %g1
2426 st %g0, [%g1]
2427 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2429 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2435 CPU_ADDR(%g1, %g2)
2436 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2437 stx %o1, [%g1 + CPU_TMP2] ! save %o1
2445 mov %o0, %g1 ! move ccr to normal %g1
2447 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2448 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1
2452 CPU_ADDR(%g1, %g2)
2453 stx %o0, [%g1 + CPU_TMP1] ! save %o0
2454 stx %o1, [%g1 + CPU_TMP2] ! save %o1
2457 mov %g1, %o1
2467 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0
2468 ldx [%g1 + CPU_TMP2], %o1 ! restore %o1
2481 rdpr %tstate, %g1 ! get tstate
2482 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr
2486 rd %fprs, %g1 ! get fprs
2487 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2503 rdpr %tstate, %g1 ! get tstate
2508 andn %g1, %g2, %g1 ! zero current user bits
2512 wrpr %g1, %g3, %tstate ! write tstate
2519 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2520 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2535 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2536 ld [%g1 + CPU_ID], %o0 ! load cpu_id
2537 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2539 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2540 sra %g1, 0, %o1
2548 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2549 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2553 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals
2554 st %l1, [%g1 + CPU_TMP2]
2563 ! Note that %g1 still contains CPU struct addr
2564 ld [%g1 + CPU_TMP2], %l1 ! restore locals
2565 ld [%g1 + CPU_TMP1], %l0
2568 mov %g1, %l0
2569 st %l1, [%g1 + CPU_TMP2]
2576 cmp %g1, OSYS_mmap ! compare to old 4.x mmap
2577 movz %icc, SYS_mmap, %g1
2590 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2591 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2593 st %l0, [%g1 + CPU_TMP1] ! save some locals
2594 st %l1, [%g1 + CPU_TMP2]
2597 mov %g1, %l1
2601 ld [%g1 + CPU_TMP1], %l0 ! restore locals
2602 ld [%g1 + CPU_TMP2], %l1
2663 mov T_DATA_EXCEPTION, %g1
2709 mov PTL1_BAD_MMUTRAP, %g1
2715 mov PTL1_BAD_MMUTRAP, %g1
2719 mov PTL1_BAD_MMUTRAP, %g1
2740 jmp %g1 + 0
2747 jmp %g1 + 0
2767 mov MMU_PCONTEXT, %g1
2768 ldxa [%g1]ASI_DMMU, %g1
2769 srlx %g1, CTXREG_NEXT_SHIFT, %g3
2773 btst %g4, %g1
2776 xor %g3, %g1, %g3 ! user: clr N_pgsz0/1 bits
2778 set DEMAP_ALL_TYPE, %g1
2779 stxa %g0, [%g1]ASI_DTLB_DEMAP
2780 stxa %g0, [%g1]ASI_ITLB_DEMAP
2781 mov MMU_PCONTEXT, %g1
2782 stxa %g3, [%g1]ASI_DMMU
2784 sethi %hi(FLUSH_ADDR), %g1
2785 flush %g1 ! flush required by immu
2862 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer
2863 srlx %g1, 32, %g6
2890 TRACE_PTR(%g1, %g6)
2892 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi
2894 stna %g6, [%g1 + TRAP_ENT_TPC]%asi
2896 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi
2897 stxa %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
2898 stxa %g0, [%g1 + TRAP_ENT_TR]%asi
2899 stxa %g0, [%g1 + TRAP_ENT_F1]%asi
2900 stxa %g0, [%g1 + TRAP_ENT_F2]%asi
2901 stxa %g0, [%g1 + TRAP_ENT_F3]%asi
2902 stxa %g0, [%g1 + TRAP_ENT_F4]%asi
2904 stha %g6, [%g1 + TRAP_ENT_TL]%asi
2906 stha %g6, [%g1 + TRAP_ENT_TT]%asi
2907 TRACE_NEXT(%g1, %g4, %g5)
2994 set fast_trap_dummy_call, %g1
3013 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
3032 mov %pc, %g1 ;\
3033 add %g1, 16, %g1 ;\