Lines Matching full:g2
80 * %g2, %g3 args for above
333 mov 8, %g2 ;\
334 sta %l2, [%sp + %g2]asi_num ;\
340 sta %l6, [%g4 + %g2]asi_num ;\
345 sta %i2, [%g4 + %g2]asi_num ;\
350 sta %i6, [%g4 + %g2]asi_num ;\
437 mov 8, %g2 ;\
440 lda [%sp + %g2]asi_num, %l2 ;\
445 lda [%g4 + %g2]asi_num, %l6 ;\
450 lda [%g4 + %g2]asi_num, %i2 ;\
455 lda [%g4 + %g2]asi_num, %i6 ;\
536 mov 8 + V9BIAS64, %g2 ;\
537 stxa %l1, [%sp + %g2]asi_num ;\
544 stxa %l5, [%g5 + %g2]asi_num ;\
549 stxa %i1, [%g5 + %g2]asi_num ;\
554 stxa %i5, [%g5 + %g2]asi_num ;\
636 mov V9BIAS64 + 8, %g2 ;\
637 ldxa [%sp + %g2]asi_num, %l1 ;\
644 ldxa [%g5 + %g2]asi_num, %l5 ;\
649 ldxa [%g5 + %g2]asi_num, %i1 ;\
654 ldxa [%g5 + %g2]asi_num, %i5 ;\
756 mov 8, %g2 ;\
757 sta %l2, [%sp + %g2]asi_num ;\
763 sta %l6, [%g4 + %g2]asi_num ;\
768 sta %i2, [%g4 + %g2]asi_num ;\
773 sta %i6, [%g4 + %g2]asi_num ;\
785 mov 8 + V9BIAS64, %g2 ;\
786 stxa %l1, [%sp + %g2]asi_num ;\
793 stxa %l5, [%g5 + %g2]asi_num ;\
798 stxa %i1, [%g5 + %g2]asi_num ;\
803 stxa %i5, [%g5 + %g2]asi_num ;\
869 or %g0, P_UTRAP4, %g2 ;\
881 or %g0, P_UTRAP10, %g2 ;\
893 or %g0, P_UTRAP11, %g2 ;\
953 rdpr %tpc, %g2 ;\
962 ldxa [MMU_TAG_ACCESS]%asi, %g2 ;\
970 ldxa [MMU_SFAR]%asi, %g2 ;\
977 ldxa [MMU_SFAR]%asi, %g2 ;\
989 ldxa [MMU_SFAR]%asi, %g2 ;\
998 ldxa [MMU_SFAR]%asi, %g2 ;\
1010 * g2 = tag access register
1019 ldxa [%g1]ASI_DMMU, %g2 ;\
1022 and %g2, %g4, %g3 /* g3 = ctx */ ;\
1027 andn %g2, %g4, %g1 /* ctx = primary */ ;\
1064 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\
1065 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1069 srax %g2, PREDISM_BASESHIFT, %g6 /* g6 > 0 ISM predicted */ ;\
1071 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1101 ldxa [%g6]ASI_DMMU, %g2 /* g2 = tag access */ ;\
1102 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1106 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1157 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\
1158 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1162 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1194 ldxa [%g6]ASI_IMMU, %g2 /* g2 = tag access */ ;\
1195 sllx %g2, TAGACC_CTX_LSHIFT, %g3 ;\
1199 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1238 * g2 = tag access register ;\
1270 * g2 = tag access register (in)
1285 stxa %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\
1575 * g2 = tag access register (in)
1584 ldxa [%g4]ASI_IMMU, %g2 ! arg1 = addr
1611 or %g2, %g0, %g7
1718 ldx [%g1 + CPU_TMP1], %g2
1751 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1753 brz,pt %g2, 1f
1756 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1758 brz,pt %g2, 1f
1760 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1791 smul %g1, CPTRSIZE, %g2
1811 ldn [%g5 + %g2], %g5
1838 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step
1840 brz,pt %g2, 1f
1843 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast
1845 brz,pt %g2, 1f
1847 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast
1849 rdpr %tstate, %g2 ! cwp for trap handler
1851 bclr TSTATE_CWP_MASK, %g2
1852 wrpr %g2, %g4, %tstate
1881 ldx [%g1 + CPU_TMP1], %g2
1897 * %g2 %fsr
1914 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr
1919 andcc %g2, %g5, %g0
2077 * Note that we need to pass %fsr in %g2 (already read above).
2131 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2134 mov 1, %g2
2135 stb %g2, [%g1 + P_FIXALIGNMENT]
2287 sethi %hi(fpu_exists), %g2 ! check fpu_exists
2288 ld [%g2 + %lo(fpu_exists)], %g2
2289 brz,a,pn %g2, 4f
2296 rdpr %tpc, %g2
2297 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction
2304 rdpr %tstate, %g2 ! %tstate in %g2
2306 srl %g2, 31, %g1 ! get asi from %tstate
2345 mov %g5, %g2 ! misaligned vaddr in %g2
2366 rdpr %tpc, %g2
2367 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction
2375 rdpr %tstate, %g2 ! %tstate in %g2
2377 srl %g2, 31, %g1 ! get asi from %tstate
2408 mov %g5, %g2 ! misaligned vaddr in %g2
2416 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2418 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2420 mov 1, %g2
2421 st %g2, [%g1]
2427 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4
2429 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0
2435 CPU_ADDR(%g1, %g2)
2440 set PSR_ICC, %g2
2441 and %o0, %g2, %o0 ! mask out the rest
2452 CPU_ADDR(%g1, %g2)
2459 sll %o1, PSR_ICC_SHIFT, %g2
2461 and %g2, %g3, %g2 ! mask out rest
2462 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2
2465 or %g3, %g2, %g3 ! or in new bits
2483 set PSR_ICC, %g2
2484 and %o0, %g2, %o0 ! mask out the rest
2487 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower
2488 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef
2489 or %o0, %g2, %o0 ! or result into psr.ef
2491 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef
2492 or %o0, %g2, %o0 ! or psr.impl/ver
2504 ! setx TSTATE_V8_UBITS, %g2
2506 sllx %g3, TSTATE_CCR_SHIFT, %g2
2508 andn %g1, %g2, %g1 ! zero current user bits
2509 set PSR_ICC, %g2
2510 and %g2, %o0, %g2 ! clear all but psr.icc bits
2511 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc
2514 set PSR_EF, %g2
2515 and %g2, %o0, %g2 ! clear all but fp enable bit
2516 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef
2519 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1
2520 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2521 ldn [%g2 + T_LWP], %g3 ! load klwp pointer
2522 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer
2523 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs
2525 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en
2535 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2537 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2538 ldn [%g2 + T_LPL], %g2 ! load lpl pointer
2539 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid
2548 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2549 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2550 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2551 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr
2552 brz,pn %g2, 1f ! has it been set?
2556 wrpr %g0, %g2, %tnpc ! setup tnpc
2590 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2
2591 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer
2592 ldn [%g2 + T_LWP], %g2 ! load klwp pointer
2600 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr
2660 ldxa [MMU_TAG_ACCESS]%asi, %g2
2764 set obp_bpt, %g2
2788 jmp %g2
2827 * g2 = tag access register (in)
2844 * g2 = tag access register (in)
2856 stxa %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access
2883 * g2 = tag access register (in)
2897 stxa %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg
3013 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\
3014 ldn [%g2 + CPU_THREAD], %g3 /* load thread pointer */ ;\
3029 * %g2: address of CPU structure \