298 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip);
299 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip);
300 static void ppb_init_hotplug(ppb_devstate_t *ppb);
372 	ppb_devstate_t *ppb;  in ppb_attach()  local
392 		ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance);  in ppb_attach()
393 		ppb->dip = devi;  in ppb_attach()
394 		mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);  in ppb_attach()
395 		ppb->ppb_soft_state = PCI_SOFT_STATE_CLOSED;  in ppb_attach()
397 			mutex_destroy(&ppb->ppb_mutex);  in ppb_attach()
401 		ppb_pwr_setup(ppb, devi);  in ppb_attach()
403 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {  in ppb_attach()
404 			mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_attach()
410 			ppb->ppb_pwr_p->pwr_fp++;  in ppb_attach()
412 			pci_pwr_change(ppb->ppb_pwr_p,  in ppb_attach()
413 			    ppb->ppb_pwr_p->current_lvl,  in ppb_attach()
414 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));  in ppb_attach()
417 		ppb->ppb_cache_line_size =  in ppb_attach()
419 		ppb->ppb_latency_timer =  in ppb_attach()
434 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {  in ppb_attach()
435 			ppb->ppb_pwr_p->pwr_fp--;  in ppb_attach()
437 			pci_pwr_change(ppb->ppb_pwr_p,  in ppb_attach()
438 			    ppb->ppb_pwr_p->current_lvl,  in ppb_attach()
439 			    pci_pwr_new_lvl(ppb->ppb_pwr_p));  in ppb_attach()
441 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_attach()
444 		ppb->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;  in ppb_attach()
445 		for (pdip = ddi_get_parent(ppb->dip); pdip && (pdip != root) &&  in ppb_attach()
446 		    (ppb->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);  in ppb_attach()
454 				ppb->parent_bus =  in ppb_attach()
463 		if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)  in ppb_attach()
469 			ppb_init_hotplug(ppb);  in ppb_attach()
473 		    ppb->hotplug_capable == B_TRUE ? "has":"has no");  in ppb_attach()
475 		ppb_fm_init(ppb);  in ppb_attach()
484 		ppb = (ppb_devstate_t *)  in ppb_attach()
487 		pci_pwr_resume(devi, ppb->ppb_pwr_p);  in ppb_attach()
498 	ppb_devstate_t *ppb;  in ppb_detach()  local
507 		ppb = (ppb_devstate_t *)  in ppb_detach()
510 		ppb_fm_fini(ppb);  in ppb_detach()
512 		if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)  in ppb_detach()
514 		else if (ppb->hotplug_capable == B_TRUE)  in ppb_detach()
524 		if (ppb->ppb_pwr_p != NULL) {  in ppb_detach()
525 			ppb_pwr_teardown(ppb, devi);  in ppb_detach()
527 		mutex_destroy(&ppb->ppb_mutex);  in ppb_detach()
533 		ppb = (ppb_devstate_t *)  in ppb_detach()
536 		pci_pwr_suspend(devi, ppb->ppb_pwr_p);  in ppb_detach()
714 	ppb_devstate_t *ppb;  in ppb_bus_power()  local
716 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in ppb_bus_power()
719 	return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result));  in ppb_bus_power()
795 	ppb_devstate_t *ppb;  in ppb_initchild()  local
843 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in ppb_initchild()
853 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {  in ppb_initchild()
858 		pci_pwr_create_info(ppb->ppb_pwr_p, child);  in ppb_initchild()
860 		ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0);  in ppb_initchild()
885 		if (PM_CAPABLE(ppb->ppb_pwr_p)) {  in ppb_initchild()
886 			pci_pwr_rm_info(ppb->ppb_pwr_p, child);  in ppb_initchild()
928 		    ppb->ppb_cache_line_size);  in ppb_initchild()
944 			latency_timer = ppb->ppb_latency_timer;  in ppb_initchild()
946 			    ppb->ppb_latency_timer);  in ppb_initchild()
968 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {  in ppb_initchild()
995 	ppb_devstate_t *ppb;  in ppb_uninitchild()  local
997 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in ppb_uninitchild()
1003 	if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {  in ppb_uninitchild()
1014 	ppb_devstate_t *ppb;  in ppb_removechild()  local
1016 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in ppb_removechild()
1019 	if (PM_CAPABLE(ppb->ppb_pwr_p)) {  in ppb_removechild()
1024 		pci_pwr_rm_info(ppb->ppb_pwr_p, dip);  in ppb_removechild()
1041 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip)  in ppb_pwr_setup()  argument
1053 	if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) {  in ppb_pwr_setup()
1058 	conf_hdl = ppb->ppb_conf_hdl;  in ppb_pwr_setup()
1063 	if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &ppb->ppb_pm_cap_ptr))  in ppb_pwr_setup()
1075 	ppb->ppb_pwr_p = (pci_pwr_t *)  in ppb_pwr_setup()
1077 	ppb->ppb_pwr_p->pwr_fp = 0;  in ppb_pwr_setup()
1079 	pmcsr_bse = PCI_CAP_GET8(conf_hdl, 0, ppb->ppb_pm_cap_ptr,  in ppb_pwr_setup()
1082 	pmcap = PCI_CAP_GET16(conf_hdl, 0, ppb->ppb_pm_cap_ptr,  in ppb_pwr_setup()
1092 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE;  in ppb_pwr_setup()
1098 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;  in ppb_pwr_setup()
1110 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));  in ppb_pwr_setup()
1111 		ppb->ppb_pwr_p = NULL;  in ppb_pwr_setup()
1128 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE;  in ppb_pwr_setup()
1131 		ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE;  in ppb_pwr_setup()
1135 	ppb->ppb_pwr_p->pwr_dip = pdip;  in ppb_pwr_setup()
1136 	mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL);  in ppb_pwr_setup()
1140 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {  in ppb_pwr_setup()
1143 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) {  in ppb_pwr_setup()
1146 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) {  in ppb_pwr_setup()
1160 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr_setup()
1161 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));  in ppb_pwr_setup()
1162 		ppb->ppb_pwr_p = NULL;  in ppb_pwr_setup()
1175 		mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr_setup()
1176 		kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));  in ppb_pwr_setup()
1177 		ppb->ppb_pwr_p = NULL;  in ppb_pwr_setup()
1182 	ppb->ppb_pwr_p->current_lvl =  in ppb_pwr_setup()
1183 	    pci_pwr_current_lvl(ppb->ppb_pwr_p);  in ppb_pwr_setup()
1190 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip)  in ppb_pwr_teardown()  argument
1197 	if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) {  in ppb_pwr_teardown()
1208 	pci_config_teardown(&ppb->ppb_conf_hdl);  in ppb_pwr_teardown()
1209 	mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr_teardown()
1210 	kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t));  in ppb_pwr_teardown()
1233 	ppb_devstate_t *ppb;  in pci_pwr_current_lvl()  local
1239 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in pci_pwr_current_lvl()
1242 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, 0,  in pci_pwr_current_lvl()
1243 	    ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)  in pci_pwr_current_lvl()
1257 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {  in pci_pwr_current_lvl()
1278 	ppb_devstate_t *ppb;  in ppb_pwr()  local
1285 	ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,  in ppb_pwr()
1287 	if (ppb == NULL) {  in ppb_pwr()
1296 	mutex_enter(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1304 	lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p);  in ppb_pwr()
1306 		pci_pwr_component_busy(ppb->ppb_pwr_p);  in ppb_pwr()
1310 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1314 		pci_pwr_component_busy(ppb->ppb_pwr_p);  in ppb_pwr()
1316 		pci_pwr_component_idle(ppb->ppb_pwr_p);  in ppb_pwr()
1319 	if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, 0,  in ppb_pwr()
1320 	    ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16)  in ppb_pwr()
1337 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) {  in ppb_pwr()
1341 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1348 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) {  in ppb_pwr()
1352 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1357 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {  in ppb_pwr()
1370 		if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) {  in ppb_pwr()
1374 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1385 		mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1400 			mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1406 	PCI_CAP_PUT16(ppb->ppb_conf_hdl, 0, ppb->ppb_pm_cap_ptr, PCI_PMCSR,  in ppb_pwr()
1429 	ppb->ppb_pwr_p->current_lvl = lvl;  in ppb_pwr()
1431 	mutex_exit(&ppb->ppb_pwr_p->pwr_mutex);  in ppb_pwr()
1445 ppb_init_hotplug(ppb_devstate_t *ppb)  in ppb_init_hotplug()  argument
1447 	ppb->hotplug_capable = B_FALSE;  in ppb_init_hotplug()
1449 	if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS,  in ppb_init_hotplug()
1453 		if (pcihp_init(ppb->dip) != DDI_SUCCESS) {  in ppb_init_hotplug()
1456 			    ddi_driver_name(ppb->dip),  in ppb_init_hotplug()
1457 			    ddi_get_instance(ppb->dip));  in ppb_init_hotplug()
1459 			ppb->hotplug_capable = B_TRUE;  in ppb_init_hotplug()
1462 	if (ppb->hotplug_capable == B_FALSE) {  in ppb_init_hotplug()
1466 		if (ddi_create_minor_node(ppb->dip, "devctl", S_IFCHR,  in ppb_init_hotplug()
1467 		    PCI_MINOR_NUM(ddi_get_instance(ppb->dip), PCI_DEVCTL_MINOR),  in ppb_init_hotplug()
1471 			    ddi_driver_name(ppb->dip),  in ppb_init_hotplug()
1472 			    ddi_get_instance(ppb->dip));  in ppb_init_hotplug()