Lines Matching refs:g4
285 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext
286 sll %g4, CTXREG_EXT_SHIFT, %g4
287 or %g6, %g4, %g6 ! %g6 = pgsz | cnum
289 set MMU_PCONTEXT, %g4
290 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
294 stxa %g6, [%g4]ASI_DMMU /* wr new ctxum */
297 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
317 set SFMMU_PGCNT_MASK, %g4
318 and %g4, %g2, %g3 /* g3 = pgcnt - 1 */
324 sethi %hi(ksfmmup), %g4
325 ldx [%g4 + %lo(ksfmmup)], %g4
326 cmp %g4, %g2
354 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext
355 sll %g4, CTXREG_EXT_SHIFT, %g4
356 or %g5, %g4, %g5
358 set MMU_PCONTEXT, %g4
359 ldxa [%g4]ASI_DMMU, %g6 /* rd old ctxnum */
363 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
376 stxa %g6, [%g4]ASI_DMMU /* restore old ctxnum */
384 set DEMAP_ALL_TYPE, %g4
385 stxa %g0, [%g4]ASI_DTLB_DEMAP
386 stxa %g0, [%g4]ASI_ITLB_DEMAP
422 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
444 DCACHE_FLUSHCOLOR(%g1, 0, %g2, %g3, %g4)
445 DCACHE_FLUSHCOLOR(%g1, 1, %g2, %g3, %g4)
446 DCACHE_FLUSHCOLOR(%g1, 2, %g2, %g3, %g4)
447 DCACHE_FLUSHCOLOR(%g1, 3, %g2, %g3, %g4)
598 PN_L2_FLUSHALL(%g3, %g4, %g5)
860 CPU_INDEX(%g1, %g4)
861 set ch_err_tl1_pending, %g4
862 ldub [%g1 + %g4], %g2
869 stb %g0, [%g1 + %g4]
886 mov PIL_15, %g4
896 mov PIL_15, %g4
998 andn %g1, DCU_DC + DCU_IC, %g4
999 stxa %g4, [%g0]ASI_DCU
1002 ASM_JMP(%g4, fast_ecc_err)
1016 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
1017 stxa %g4, [%g0]ASI_ESTATE_ERR
1030 PARK_SIBLING_CORE(%g1, %g5, %g4)
1046 and %g3, EN_REG_CEEN + EN_REG_NCEEN, %g4
1048 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1055 PN_L2_FLUSHALL(%g4, %g5, %g6)
1057 CPU_INDEX(%g4, %g5)
1058 mulx %g4, CPU_NODE_SIZE, %g4
1060 add %g4, %g5, %g4
1061 ld [%g4 + ECACHE_LINESIZE], %g5
1062 ld [%g4 + ECACHE_SIZE], %g4
1065 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
1088 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1096 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1140 rdpr %pil, %g4
1141 cmp %g4, PIL_14
1143 movl %icc, PIL_14, %g4
1300 andn %g1, DCU_IC, %g4
1301 stxa %g4, [%g0]ASI_DCU
1314 PARK_SIBLING_CORE(%g1, %g5, %g4)
1329 clr %g4 ! TL=0 bit in afsr
1331 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1346 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1354 UNPARK_SIBLING_CORE(%g1, %g5, %g4)
1398 rdpr %pil, %g4
1399 cmp %g4, PIL_14
1401 movl %icc, PIL_14, %g4
1469 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
1470 stxa %g4, [%g0]ASI_ESTATE_ERR
1482 andn %g1, DCU_IC + DCU_DC, %g4
1483 stxa %g4, [%g0]ASI_DCU
1496 PARK_SIBLING_CORE(%g1, %g6, %g4)
1516 sllx %g5, CLO_FLAGS_TT_SHIFT, %g4
1518 and %g4, %g2, %g4 ! ttype
1519 or %g6, %g4, %g4 ! TT and TL
1521 or %g3, %g4, %g4 ! TT and TL and CEEN
1523 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
1533 sllx %g4, 32, %g4
1534 or %g4, %g3, %g3
1549 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
1608 RESET_USER_RTT_REGS(%g4, %g5, async_err_resetskip)
1612 mov PIL_15, %g4 ! run at pil 15
1632 mov PIL_15, %g4 ! run at pil 15
1697 ld [%g6 + TRAPTR_OFFSET], %g4
1698 add %g5, %g4, %g5
1705 rd STICK, %g4
1706 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
1707 rdpr %tl, %g4
1708 stha %g4, [%g5 + TRAP_ENT_TL]%asi
1709 rdpr %tt, %g4
1710 stha %g4, [%g5 + TRAP_ENT_TT]%asi
1711 rdpr %tpc, %g4
1712 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
1713 rdpr %tstate, %g4
1714 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
1727 ld [%g6 + TRAPTR_LIMIT], %g4
1730 sub %g4, TRAP_ENT_SIZE, %g4
1731 cmp %g5, %g4
1747 mov 1, %g4
1748 sllx %g4, DCU_PE_SHIFT, %g4
1749 andn %g3, %g4, %g3
1778 mov PIL_15, %g4 ! run at pil 15
1842 ld [%g6 + TRAPTR_OFFSET], %g4
1843 add %g5, %g4, %g5
1850 rd STICK, %g4
1851 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
1852 rdpr %tl, %g4
1853 stha %g4, [%g5 + TRAP_ENT_TL]%asi
1854 rdpr %tt, %g4
1855 stha %g4, [%g5 + TRAP_ENT_TT]%asi
1856 rdpr %tpc, %g4
1857 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
1858 rdpr %tstate, %g4
1859 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
1872 ld [%g6 + TRAPTR_LIMIT], %g4
1875 sub %g4, TRAP_ENT_SIZE, %g4
1876 cmp %g5, %g4
1981 jmp %g4 + 4
2079 rd STICK, %g4 ! read stick reg
2080 add %g4, %o0, %o1 ! adjust stick with skew
2216 ! %g4 - ptr. to scrub_misc chsm_outstanding[index].
2223 GET_CPU_PRIVATE_PTR(%g2, %g4, %g5, 1f);
2224 ld [%g4], %g2 ! cpu's chsm_outstanding[index]
2231 st %g3, [%g4] ! delay - store incremented counter
2547 set MMU_TAG_ACCESS, %g4
2548 stxa %o2, [%g4]ASI_IMMU