59 #define	ECACHE_FLUSHALL(arg1, arg2, arg3, tmp1)				\  argument
529 #define	FLUSH_ALL_TLB(tmp1)					\  argument
530 	set	DEMAP_ALL_TYPE, tmp1				;\
531 	stxa	%g0, [tmp1]ASI_ITLB_DEMAP			;\
532 	stxa	%g0, [tmp1]ASI_DTLB_DEMAP			;\
533 	sethi	%hi(FLUSH_ADDR), tmp1				;\
534 	flush	tmp1
634 #define	UPDATE_STICK_COMPARE(tmp1, tmp2)			\  argument
635 	CPU_ADDR(tmp1, tmp2)					;\
636 	lduh	[tmp1 + CPU_FLAGS], tmp2			;\
639 	rd	STICK, tmp1					;\
640 	add	tmp1, tmp2, tmp1				;\
643 	or	tmp1, tmp2, tmp2				;\
644 	movnz	%xcc, tmp1, tmp2				;\
652 #define	IAG_CRE(tmp1, tmp2)					\  argument
653 	set	OPL_SCRATCHPAD_ERRLOG, tmp1			;\
654 	ldxa	[tmp1]ASI_SCRATCHPAD, tmp1			;\
655 	srlx	tmp1, ERRLOG_REG_EIDR_SHIFT, tmp1		;\
657 	and	tmp1, tmp2, tmp1				;\
658 	stxa	tmp1, [%g0]ASI_EIDR				;\
660 	sethi	%hi(hres_last_tick), tmp1			;\
661 	ldx	[tmp1 + %lo(hres_last_tick)], tmp1		;\
663 	add	tmp1, tmp2, tmp1				;\
664 	wr	tmp1, %g0, STICK				;\
665 	UPDATE_STICK_COMPARE(tmp1, tmp2)
724 #define	CLEAR_GEN_REGS(tmp1, label)				\  argument
725 	set	TSTATE_KERN, tmp1				;\
726 	wrpr	%g0, tmp1, %tstate				;\
758 	rdpr	%tl, tmp1					;\
759 	cmp	tmp1, 1						;\
761 	 rdpr	%pstate, tmp1					;\
762 	wrpr	tmp1, PSTATE_AG|PSTATE_IG, %pstate		;\
764 	rdpr	%pstate, tmp1					;\
765 	wrpr	tmp1, PSTATE_IG|PSTATE_MG, %pstate		;\
767 	rdpr	%pstate, tmp1					;\
768 	wrpr	tmp1, PSTATE_MG|PSTATE_AG, %pstate		;\
772 	wrpr	tmp1, PSTATE_AG, %pstate			;\
774 	rdpr	%pstate, tmp1					;\
775 	wrpr	tmp1, PSTATE_AG, %pstate			;\
795 #define	RESET_PREV_TSTATE(tmp1, tmp2, label)			\  argument
796 	rdpr	%tl, tmp1					;\
797 	subcc	tmp1, 1, tmp1					;\
800 	wrpr	tmp1, %g0, %tl					;\
805 	add	tmp1, 1, tmp1					;\
806 	wrpr	tmp1, %g0, %tl					;\
831 #define	RESET_MMU_REGS(tmp1, tmp2, tmp3)			\  argument
832 	FLUSH_ALL_TLB(tmp1)					;\
833 	set	MMU_PCONTEXT, tmp1				;\
836 	stxa	tmp2, [tmp1]ASI_DMMU				;\
837 	set	MMU_SCONTEXT, tmp1				;\
838 	stxa	tmp2, [tmp1]ASI_DMMU				;\
839 	sethi	%hi(ktsb_base), tmp1				;\
840 	ldx	[tmp1 + %lo(ktsb_base)], tmp2			;\
845 	RESET_WINREG(tmp1)
930 #define	RESET_TO_PRIV(tmp, tmp1, tmp2, local)			\  argument
931 	RESET_MMU_REGS(tmp, tmp1, tmp2)				;\
932 	CPU_ADDR(tmp, tmp1)					;\
943 	rdpr	%cwp, tmp1					;\
944 	or	tmp, tmp1, tmp					;\
1410 #define	RESTORE_WREGS(tmp1, tmp2)		\  argument
1411 	CPU_INDEX(tmp1, tmp2)			;\
1414 	sllx	tmp1, 7, tmp1			;\
1415 	add	tmp2, tmp1, tmp2		;\
1433 #define	SAVE_WREGS(tmp1, tmp2)			\  argument
1434 	CPU_INDEX(tmp1, tmp2)			;\
1437 	sllx	tmp1, 7, tmp1			;\
1438 	add	tmp2, tmp1, tmp2		;\