Lines Matching refs:g0
98 stxa %g0, [%o0]ASI_DTLB_DEMAP /* dmmu flush for KCONTEXT */
99 stxa %g0, [%o0]ASI_ITLB_DEMAP /* immu flush for KCONTEXT */
102 wrpr %g0, %o5, %pstate /* enable interrupts */
117 wrpr %g0, 1, %tl
126 stxa %g0, [%o0]ASI_DTLB_DEMAP
127 stxa %g0, [%o0]ASI_ITLB_DEMAP
130 wrpr %g0, 0, %tl
133 wrpr %g0, %o5, %pstate /* enable interrupts */
143 stxa %g0, [%g1]ASI_DTLB_DEMAP
144 stxa %g0, [%g1]ASI_ITLB_DEMAP
171 stxa %g0, [%g1]ASI_DTLB_DEMAP
172 stxa %g0, [%g1]ASI_ITLB_DEMAP
190 stxa %g0, [%g1]ASI_DTLB_DEMAP
191 stxa %g0, [%g1]ASI_ITLB_DEMAP
230 stxa %g0, [%g1]ASI_DTLB_DEMAP
231 stxa %g0, [%g1]ASI_ITLB_DEMAP
263 stxa %g0, [%g1]ASI_DTLB_DEMAP
264 stxa %g0, [%g1]ASI_ITLB_DEMAP
281 stxa %g0, [%g4]ASI_DTLB_DEMAP
282 stxa %g0, [%g4]ASI_ITLB_DEMAP
320 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1
348 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1
392 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch
460 wr %g0, TRAPTR_ASI, %asi; \
472 stna %g0, [ptr + TRAP_ENT_TR]%asi; \
473 stna %g0, [ptr + TRAP_ENT_F1]%asi; \
474 stna %g0, [ptr + TRAP_ENT_F2]%asi; \
475 stna %g0, [ptr + TRAP_ENT_F3]%asi; \
476 stna %g0, [ptr + TRAP_ENT_F4]%asi; \
477 wr %g0, scr2, %asi; \
504 stxa reg1, [%g0]ASI_SCRATCHPAD ;\
519 ldxa [%g0]ASI_SCRATCHPAD, reg1
531 stxa %g0, [tmp1]ASI_ITLB_DEMAP ;\
532 stxa %g0, [tmp1]ASI_DTLB_DEMAP ;\
637 andcc tmp2, CPU_ENABLE, %g0 ;\
645 wr tmp2, %g0, STICK_COMPARE
658 stxa tmp1, [%g0]ASI_EIDR ;\
659 wr %g0, 0, SOFTINT ;\
664 wr tmp1, %g0, STICK ;\
669 wr %g0, FPRS_FEF, %fprs ;\
670 wr %g0, %g0, %gsr ;\
706 wr %g0, %g0, %fprs
709 mov %g0, %g1 ;\
710 mov %g0, %g2 ;\
711 mov %g0, %g3 ;\
712 mov %g0, %g4 ;\
713 mov %g0, %g5 ;\
714 mov %g0, %g6 ;\
715 mov %g0, %g7
726 wrpr %g0, tmp1, %tstate ;\
727 mov %g0, %y ;\
728 mov %g0, %asi ;\
729 mov %g0, %ccr ;\
730 mov %g0, %l0 ;\
731 mov %g0, %l1 ;\
732 mov %g0, %l2 ;\
733 mov %g0, %l3 ;\
734 mov %g0, %l4 ;\
735 mov %g0, %l5 ;\
736 mov %g0, %l6 ;\
737 mov %g0, %l7 ;\
738 mov %g0, %i0 ;\
739 mov %g0, %i1 ;\
740 mov %g0, %i2 ;\
741 mov %g0, %i3 ;\
742 mov %g0, %i4 ;\
743 mov %g0, %i5 ;\
744 mov %g0, %i6 ;\
745 mov %g0, %i7 ;\
746 mov %g0, %o1 ;\
747 mov %g0, %o2 ;\
748 mov %g0, %o3 ;\
749 mov %g0, %o4 ;\
750 mov %g0, %o5 ;\
751 mov %g0, %o6 ;\
752 mov %g0, %o7 ;\
753 mov %g0, %o0 ;\
754 mov %g0, %g4 ;\
755 mov %g0, %g5 ;\
756 mov %g0, %g6 ;\
757 mov %g0, %g7 ;\
785 wrpr %g0, tmp, %cwp ;\
786 wrpr %g0, tmp, %cleanwin ;\
788 wrpr %g0, tmp, %cansave ;\
789 wrpr %g0, %g0, %canrestore ;\
790 wrpr %g0, %g0, %otherwin ;\
791 wrpr %g0, PIL_MAX, %pil ;\
792 wrpr %g0, WSTATE_KERN, %wstate
800 wrpr tmp1, %g0, %tl ;\
802 wrpr tmp2, %g0, %tstate ;\
803 wrpr %g0, %g0, %tpc ;\
804 wrpr %g0, %g0, %tnpc ;\
806 wrpr tmp1, %g0, %tl ;\
816 wrpr %g0, tmp, %tstate ;\
817 wrpr %g0, 0, %tpc ;\
818 wrpr %g0, 0, %tnpc ;\
849 stxa %g0, [tmp]ASI_IMMU ;\
850 stxa %g0, [tmp]ASI_DMMU ;\
861 stxa %g0, [tmp]ASI_ITSB_PREFETCH ;\
863 stxa %g0, [tmp]ASI_ITSB_PREFETCH ;\
865 stxa %g0, [tmp]ASI_ITSB_PREFETCH ;\
867 stxa %g0, [tmp]ASI_ITSB_PREFETCH ;\
869 stxa %g0, [tmp]ASI_DTSB_PREFETCH ;\
871 stxa %g0, [tmp]ASI_DTSB_PREFETCH ;\
873 stxa %g0, [tmp]ASI_DTSB_PREFETCH ;\
875 stxa %g0, [tmp]ASI_DTSB_PREFETCH
885 stxa %g0, [tmp]ASI_DMMU
941 wrpr %g0, 1, %tl ;\
945 wrpr tmp, %g0, %tstate ;\
946 wrpr %g0, %tpc
960 andcc %g1, ASI_ECR_RTE_UE | ASI_ECR_RTE_CEDG, %g0
973 sub %g0, 1, %g4
985 sub %g0, 1, %g4
1000 sub %g0, 1, %g4
1079 andcc %g1, SFSR_FV, %g0
1084 andcc %g1, %g3, %g0 ! Check for UE/BERR/TO errors
1092 andcc %g1, SFSR_FV, %g0
1099 andcc %g1, %g3, %g0 ! Check UE/BERR/TO for valid SFPAR
1104 andcc %g1, %g3, %g0
1116 subcc %g3, 1, %g0 ! Subtract one from the count
1128 andcc %g1, %g3, %g0
1159 andcc %g5, SFSR_FV, %g0 ! see if SFSR.FV is valid
1162 andcc %g5, %g2, %g0 ! check for UE
1236 andcc %g1, %g2, %g0 ! Check for Multi-errs
1248 andcc %g1, %g2, %g0 ! errors i.e.IUG_DTLB,
1297 andcc %g1, %g2, %g0
1310 andcc %g1, %g2, %g0
1325 andcc %g1, %g2, %g0
1346 andcc %g1, %g2, %g0
1355 andcc %g1, %g2, %g0
1364 andcc %g1, %g2, %g0
1373 andcc %g1, %g2, %g0
1468 sub %g0, 1, %g4
1486 sub %g0, 1, %g4
1559 wrpr %g0, %g3, %pstate ! turn off interrupts
1566 wr %o1, %g0, STICK ! write stick reg
1576 mov %g0, %o0
1584 wrpr %g0, %l2, %pstate ! protect our FPU diddling
1587 andcc %l0, FPRS_FEF, %g0
1589 wr %g0, FPRS_FEF, %fprs ! ... enable the fpu
1605 stn %g0, [THREAD_REG + T_LOFAULT] ! remove the lofault handler
1608 wr %g0, %l0, %fprs ! restore %fprs
1613 wrpr %g0, %l1, %pstate ! restore interrupts
1616 restore %g0, %g0, %o0
1620 stn %g0, [THREAD_REG + T_LOFAULT] ! remove the lofault handler
1623 wr %g0, %l0, %fprs ! restore %fprs
1628 wrpr %g0, %l1, %pstate ! restore interrupts
1637 restore %g0, -1, %o0
1656 ldxa [%g0]ASI_EIDR, %o2
1689 stxa %g0, [%o0]ASI_DTLB_DEMAP
1690 stxa %g0, [%o0]ASI_ITLB_DEMAP
1708 ldxa [%g0] ASI_DEVICE_SERIAL_ID, %o2
1728 wrpr %g0, %g3, %pstate /* interrupts */
1752 wrpr %g0, %g1, %pstate /* restore processor state */