91 		vis_inst_type	inst;  in vis_fpu_simulator()  member
100 	if ((f.inst.opf & 1) == 0) {		/* double precision */  in vis_fpu_simulator()
109 	switch (f.inst.opf) {  in vis_fpu_simulator()
123 		ftt = vis_edge(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
128 		ftt = vis_array(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
132 		ftt = vis_alignaddr(pfpsd, f.inst, pregs, prw, fp);  in vis_fpu_simulator()
135 		ftt = vis_bmask(pfpsd, f.inst, pregs, prw, fp);  in vis_fpu_simulator()
145 		ftt = vis_fcmp(pfpsd, f.inst, pregs, prw);  in vis_fpu_simulator()
154 		ftt = vis_fmul(pfpsd, f.inst);  in vis_fpu_simulator()
161 		ftt = vis_fpixel(pfpsd, f.inst, fp);  in vis_fpu_simulator()
165 		ftt = vis_pdist(pfpsd, pinst, pregs, prw, f.inst.opf);  in vis_fpu_simulator()
181 		ftt = vis_fpaddsub(pfpsd, f.inst);  in vis_fpu_simulator()
356 		ftt = vis_siam(pfpsd, f.inst, fp);  in vis_fpu_simulator()
373 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_edge()  argument
385 	nrs1 = inst.rs1;  in vis_edge()
386 	nrs2 = inst.rs2;  in vis_edge()
387 	nrd = inst.rd;  in vis_edge()
406 	switch (inst.opf) {  in vis_edge()
412 		switch (inst.opf) {  in vis_edge()
415 			if (inst.opf == edge8) {  in vis_edge()
428 			if (inst.opf == edge8l) {  in vis_edge()
447 		switch (inst.opf) {  in vis_edge()
450 			if (inst.opf == edge16) {  in vis_edge()
465 			if (inst.opf == edge16l) {  in vis_edge()
488 		switch (inst.opf) {  in vis_edge()
491 			if (inst.opf == edge32) {  in vis_edge()
506 			if (inst.opf == edge32l) {  in vis_edge()
525 	switch (inst.opf) {  in vis_edge()
550 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_array()  argument
561 	nrs1 = inst.rs1;  in vis_array()
562 	nrs2 = inst.rs2;  in vis_array()
563 	nrd = inst.rd;  in vis_array()
590 	switch (inst.opf) {  in vis_array()
615 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_alignaddr()  argument
625 	nrs1 = inst.rs1;  in vis_alignaddr()
626 	nrs2 = inst.rs2;  in vis_alignaddr()
627 	nrd = inst.rd;  in vis_alignaddr()
643 	if (inst.opf == alignaddrl) {  in vis_alignaddr()
662 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_bmask()  argument
672 	nrs1 = inst.rs1;  in vis_bmask()
673 	nrs2 = inst.rs2;  in vis_bmask()
674 	nrd = inst.rd;  in vis_bmask()
700 	vis_inst_type	inst)	/* FPU instruction to simulate. */  in vis_fpaddsub()  argument
714 	nrs1 = inst.rs1;  in vis_fpaddsub()
715 	nrs2 = inst.rs2;  in vis_fpaddsub()
716 	nrd = inst.rd;  in vis_fpaddsub()
717 	if ((inst.opf & 1) == 0) {	/* double precision */  in vis_fpaddsub()
725 	switch (inst.opf) {  in vis_fpaddsub()
796 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_fcmp()  argument
810 	nrs1 = inst.rs1;  in vis_fcmp()
811 	nrs2 = inst.rs2;  in vis_fcmp()
812 	nrd = inst.rd;  in vis_fcmp()
821 	switch (inst.opf) {  in vis_fcmp()
905 	vis_inst_type	inst)	/* FPU instruction to simulate. */  in vis_fmul()  argument
924 	nrs1 = inst.rs1;  in vis_fmul()
925 	nrs2 = inst.rs2;  in vis_fmul()
926 	nrd = inst.rd;  in vis_fmul()
927 	if ((inst.opf & 1) == 0) {	/* double precision */  in vis_fmul()
932 	switch (inst.opf) {  in vis_fmul()
1056 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_fpixel()  argument
1077 	nrs1 = inst.rs1;  in vis_fpixel()
1078 	nrs2 = inst.rs2;  in vis_fpixel()
1079 	nrd = inst.rd;  in vis_fpixel()
1080 	if ((inst.opf != fpack16) && (inst.opf != fpackfix)) {  in vis_fpixel()
1085 	switch (inst.opf) {  in vis_fpixel()
1351 	vis_inst_type	inst,	/* FPU instruction to simulate. */  in vis_siam()  argument
1356 	nrs2 = inst.rs2;  in vis_siam()
1378 		vis_inst_type	inst;  in vis_fldst()  member
1397 			return (vis_prtl_fst(pfpsd, i.inst, pregs,  in vis_fldst()
1407 			return (vis_short_fls(pfpsd, i.inst, pregs,  in vis_fldst()
1419 			return (vis_blk_fldst(pfpsd, i.inst, pregs,  in vis_fldst()
1432 	vis_inst_type	inst,	/* ISE instruction to simulate. */  in vis_prtl_fst()  argument
1450 	nrs1 = inst.rs1;  in vis_prtl_fst()
1451 	nrs2 = inst.rs2;  in vis_prtl_fst()
1452 	nrd = inst.rd;  in vis_prtl_fst()
1455 	opf = inst.opf;  in vis_prtl_fst()
1594 	vis_inst_type	inst,	/* ISE instruction to simulate. */  in vis_short_fls()  argument
1610 		vis_inst_type	inst;  in vis_short_fls()  member
1617 	nrs1 = inst.rs1;  in vis_short_fls()
1618 	nrs2 = inst.rs2;  in vis_short_fls()
1619 	nrd = inst.rd;  in vis_short_fls()
1622 	opf = inst.opf;  in vis_short_fls()
1623 	fp.inst = inst;  in vis_short_fls()
1633 		fp.inst = inst;  in vis_short_fls()
1649 		if ((inst.op3 & 7) == 3) {	/* load byte */  in vis_short_fls()
1666 		if ((inst.op3 & 7) == 3) {	/* load short */  in vis_short_fls()
1683 		if ((inst.op3 & 7) == 3) {	/* load short */  in vis_short_fls()
1713 	vis_inst_type	inst,	/* ISE instruction to simulate. */  in vis_blk_fldst()  argument
1727 		vis_inst_type	inst;  in vis_blk_fldst()  member
1733 	nrs1 = inst.rs1;  in vis_blk_fldst()
1734 	nrs2 = inst.rs2;  in vis_blk_fldst()
1735 	nrd = inst.rd;  in vis_blk_fldst()
1743 	opf = inst.opf;  in vis_blk_fldst()
1753 		fp.inst = inst;  in vis_blk_fldst()
1777 		if ((inst.op3 & 7) == 3) {	/* lddf */  in vis_blk_fldst()
1874 			fp_inst_type	inst;  in vis_wrgsr()  member
1878 		fp.inst = pinst;		/* Extract simm13 field */  in vis_wrgsr()