Lines Matching full:msi
236 * MSI Definitions
238 * MSI - Message Signaled Interrupt
242 * A device signals an interrupt via MSI using a posted
245 * The MSI capability data structure contains fields for
247 * sending an MSI message on the bus. MSI-X is an extended
248 * form of MSI, but uses the same mechanism for signaling
249 * the interrupt as MSI. For the purposes of this document,
250 * the term "MSI" refers to MSI or MSI-X.
252 * Root complexes that support MSI define an address range
255 * SUN4V/pci requirements for MSI:
260 * write to signal an MSI.
263 * ranges as signaling an MSI, however, only the data
264 * value used in the posted write signals the MSI.
267 * MSI EQ - MSI Event Queue
269 * The MSI Event Queue is a page-aligned main memory data
270 * structure used to store MSI data records.
272 * Each root port supports several MSI EQs, and each EQ has a
274 * (individually) to any cpu. The number of MSI EQs supported
276 * Each MSI EQ must be large enough to contain all possible MSI
278 * of entries in each MSI EQ is described by a property defined
281 * Each MSI EQ is compliant with the definition of interrupt
287 * generate a system interrupt when the MSI EQ is non-empty.
289 * MSI/Message/INTx Data Record format
322 * 0000 - Not an MSI data record - reserved for sw use.
333 * 1111 - Not an MSI data record - reserved for sw use.
347 * RR..RR is the requester ID of the device that initiated the MSI/MSG
362 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero.
365 * DD..DD is the MSI/MSG data or INTx number
367 * For MSI-X, bits 31..0 contain the data from the MSI packet
368 * which is the msi-number. bits 63..32 shall be zero.
370 * For MSI, bits 15..0 contain the data from the MSI message
371 * which is the msi-number. bits 63..16 shall be zero
409 * msinum - A value defining which MSI is being used.
412 * MSI-EQ.
415 * MSI-EQ.
421 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining
422 * which MSI EQ within the device is being used.
440 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered
496 } msi; member
523 /* MSI state */
526 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */
529 /* MSI valid */