Lines Matching +full:sound +full:- +full:name +full:- +full:prefix
17 * information: Portions Copyright [yyyy] [name of copyright owner]
93 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1))))
94 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1)))
112 * 1275 "bus-range" property of a PCI Bus node.
113 * DAF - should be in generic include file...
167 uchar_t *name; member
175 char *name; member
368 { 0x201, "token-ring" },
373 { 0x401, "sound" },
387 { 0x800, "interrupt-controller" },
388 { 0x801, "dma-controller" },
397 { 0xc01, "access-bus" },
400 { 0xc04, "fibre-channel" },
545 DEBUG0("PCI configurator installed - Fcode Interpretation/21554\n"); in _init()
634 regs->pcie_dev = 0; in pcicfg_pcie_dev()
646 regs->pcie_dev = 1; in pcicfg_pcie_dev()
664 int port_type = -1; in pcicfg_pcie_port_type()
736 "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { in pcicfg_configure()
737 DEBUG0("no bus-range property\n"); in pcicfg_configure()
775 * we don't expect to see a non-present in pcicfg_configure()
812 "ari-enabled", NULL, 0); in pcicfg_configure()
823 DEBUG0("Next Function - ARI Device\n"); in pcicfg_configure()
832 DEBUG0("Next Function - " in pcicfg_configure()
841 DEBUG1("Next Function - %x\n", func); in pcicfg_configure()
879 * probe handle - if not, no harm in calling this. in pcicfg_configure()
940 if (pcicfg_set_busnode_props(new_device, pcie_device_type, -1, -1) != in pcicfg_configure_ntbridge()
956 DEBUG1("ntbridge bus range start ->[%d]\n", next_bus); in pcicfg_configure_ntbridge()
966 "bus-range", bus_range, 2) != DDI_SUCCESS) { in pcicfg_configure_ntbridge()
967 DEBUG0("Cannot set ntbridge bus-range property"); in pcicfg_configure_ntbridge()
985 "pcicfg: Fail: can\'t load non-transparent bridge \ in pcicfg_configure_ntbridge()
1073 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, in pcicfg_configure_ntbridge()
1075 DEBUG0("Failed to read bus-range property\n"); in pcicfg_configure_ntbridge()
1081 bus[0], bus[1] - bus[0] + 1); in pcicfg_configure_ntbridge()
1084 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), in pcicfg_configure_ntbridge()
1104 entry->memory_len = 0; in pcicfg_configure_ntbridge()
1105 entry->io_len = 0; in pcicfg_configure_ntbridge()
1139 mem_request = &phdl->mem_req; in pcicfg_ntbridge_allocate_resources()
1140 io_request = &phdl->io_req; in pcicfg_ntbridge_allocate_resources()
1142 phdl->error = PCICFG_SUCCESS; in pcicfg_ntbridge_allocate_resources()
1149 phdl->memory_len = 0; in pcicfg_ntbridge_allocate_resources()
1152 mem_request->ra_boundbase = boundbase; in pcicfg_ntbridge_allocate_resources()
1153 mem_request->ra_boundlen = boundbase + boundlen; in pcicfg_ntbridge_allocate_resources()
1154 mem_request->ra_len = boundlen; in pcicfg_ntbridge_allocate_resources()
1155 mem_request->ra_align_mask = in pcicfg_ntbridge_allocate_resources()
1156 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ in pcicfg_ntbridge_allocate_resources()
1157 mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; in pcicfg_ntbridge_allocate_resources()
1160 * mem_request->ra_len = in pcicfg_ntbridge_allocate_resources()
1161 * PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN); in pcicfg_ntbridge_allocate_resources()
1164 phdl->memory_base = phdl->memory_last = boundbase; in pcicfg_ntbridge_allocate_resources()
1165 phdl->memory_len = boundlen; in pcicfg_ntbridge_allocate_resources()
1166 phdl->mem_hole.start = phdl->memory_base; in pcicfg_ntbridge_allocate_resources()
1167 phdl->mem_hole.len = mem_request->ra_len; in pcicfg_ntbridge_allocate_resources()
1168 phdl->mem_hole.next = (hole_t *)NULL; in pcicfg_ntbridge_allocate_resources()
1171 boundlen, mem_request->ra_len); in pcicfg_ntbridge_allocate_resources()
1188 phdl->io_len = 0; in pcicfg_ntbridge_allocate_resources()
1191 io_request->ra_len = boundlen; in pcicfg_ntbridge_allocate_resources()
1192 io_request->ra_align_mask = in pcicfg_ntbridge_allocate_resources()
1193 PCICFG_IOGRAN - 1; /* 4K alignment on I/O space */ in pcicfg_ntbridge_allocate_resources()
1194 io_request->ra_boundbase = boundbase; in pcicfg_ntbridge_allocate_resources()
1195 io_request->ra_boundlen = boundbase + boundlen; in pcicfg_ntbridge_allocate_resources()
1196 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; in pcicfg_ntbridge_allocate_resources()
1199 * io_request->ra_len = in pcicfg_ntbridge_allocate_resources()
1200 * PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN); in pcicfg_ntbridge_allocate_resources()
1203 phdl->io_base = phdl->io_last = (uint32_t)boundbase; in pcicfg_ntbridge_allocate_resources()
1204 phdl->io_len = (uint32_t)boundlen; in pcicfg_ntbridge_allocate_resources()
1205 phdl->io_hole.start = phdl->io_base; in pcicfg_ntbridge_allocate_resources()
1206 phdl->io_hole.len = io_request->ra_len; in pcicfg_ntbridge_allocate_resources()
1207 phdl->io_hole.next = (hole_t *)NULL; in pcicfg_ntbridge_allocate_resources()
1210 boundlen, io_request->ra_len); in pcicfg_ntbridge_allocate_resources()
1213 phdl->memory_base, phdl->memory_len); in pcicfg_ntbridge_allocate_resources()
1215 phdl->io_base, phdl->io_len); in pcicfg_ntbridge_allocate_resources()
1250 range[1].child_lo = range[1].parent_lo = (uint32_t)entry->memory_base; in pcicfg_ntbridge_configure_done()
1254 range[0].child_lo = range[0].parent_lo = (uint32_t)entry->io_base; in pcicfg_ntbridge_configure_done()
1258 "bus-range", (caddr_t)&bus_range, (int *)&len) != DDI_SUCCESS) { in pcicfg_ntbridge_configure_done()
1259 DEBUG0("no bus-range property\n"); in pcicfg_ntbridge_configure_done()
1264 if (entry->highest_bus) { /* secondary bus number */ in pcicfg_ntbridge_configure_done()
1265 if (entry->highest_bus < bus_range.lo) { in pcicfg_ntbridge_configure_done()
1268 bus_range.lo, entry->highest_bus); in pcicfg_ntbridge_configure_done()
1269 new_bus_range[1] = bus_range.lo + entry->highest_bus; in pcicfg_ntbridge_configure_done()
1272 new_bus_range[1] = entry->highest_bus; in pcicfg_ntbridge_configure_done()
1281 "bus-range", new_bus_range, 2) != DDI_SUCCESS) { in pcicfg_ntbridge_configure_done()
1282 DEBUG0("Failed to set bus-range property"); in pcicfg_ntbridge_configure_done()
1283 entry->error = PCICFG_FAILURE; in pcicfg_ntbridge_configure_done()
1290 unused = pcicfg_unused_space(&entry->io_hole, &len); in pcicfg_ntbridge_configure_done()
1296 range[0].size_lo = entry->io_len; in pcicfg_ntbridge_configure_done()
1299 entry->error = PCICFG_FAILURE; in pcicfg_ntbridge_configure_done()
1306 unused = pcicfg_unused_space(&entry->mem_hole, &len); in pcicfg_ntbridge_configure_done()
1312 range[1].size_lo = entry->memory_len; in pcicfg_ntbridge_configure_done()
1315 entry->error = PCICFG_FAILURE; in pcicfg_ntbridge_configure_done()
1334 "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { in pcicfg_ntbridge_unconfigure_child()
1335 DEBUG0("no bus-range property\n"); in pcicfg_ntbridge_unconfigure_child()
1387 if (entry->memory_len) in pcicfg_ntbridge_unconfigure()
1390 entry->memory_len); in pcicfg_ntbridge_unconfigure()
1393 if (entry->io_len) in pcicfg_ntbridge_unconfigure()
1396 entry->io_len); in pcicfg_ntbridge_unconfigure()
1400 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, in pcicfg_ntbridge_unconfigure()
1402 DEBUG0("ntbridge: Failed to read bus-range property\n"); in pcicfg_ntbridge_unconfigure()
1407 bus[0], bus[1] - bus[0] + 1); in pcicfg_ntbridge_unconfigure()
1410 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), in pcicfg_ntbridge_unconfigure()
1430 entry->memory_len = 0; in pcicfg_ntbridge_unconfigure()
1431 entry->io_len = 0; in pcicfg_ntbridge_unconfigure()
1503 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_get_ntbridge_child_range()
1505 DEBUG1("Failed to get assigned-addresses property %llx\n", dip); in pcicfg_get_ntbridge_child_range()
1657 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "ari-enabled"); in pcicfg_unconfigure()
1693 * free pcie_bus_t for the sub-tree in pcicfg_teardown_device()
1704 * tear down a sub-tree. in pcicfg_teardown_device()
1722 for (entry = pcicfg_phdl_list; entry != NULL; entry = entry->next) { in pcicfg_find_phdl()
1723 if (entry->dip == dip) { in pcicfg_find_phdl()
1731 * Did'nt find entry - create one in pcicfg_find_phdl()
1744 new->dip = dip; in pcicfg_create_phdl()
1746 new->next = pcicfg_phdl_list; in pcicfg_create_phdl()
1761 entry = entry->next) { in pcicfg_destroy_phdl()
1762 if (entry->dip == dip) { in pcicfg_destroy_phdl()
1764 pcicfg_phdl_list = entry->next; in pcicfg_destroy_phdl()
1766 follow->next = entry->next; in pcicfg_destroy_phdl()
1773 if (entry->memory_len > 0) { in pcicfg_destroy_phdl()
1775 entry->memory_base, in pcicfg_destroy_phdl()
1776 entry->memory_len, in pcicfg_destroy_phdl()
1779 pcicfg_free_hole(&entry->mem_hole); in pcicfg_destroy_phdl()
1781 if (entry->io_len > 0) { in pcicfg_destroy_phdl()
1783 entry->io_base, in pcicfg_destroy_phdl()
1784 entry->io_len, in pcicfg_destroy_phdl()
1787 pcicfg_free_hole(&entry->io_hole); in pcicfg_destroy_phdl()
1835 if (phdl->error != PCICFG_SUCCESS) { in pcicfg_program_ap()
1838 return (phdl->error); in pcicfg_program_ap()
1845 * it will not de-allocate assigned resources. in pcicfg_program_ap()
1849 entry->memory_len = entry->io_len = 0; in pcicfg_program_ap()
1887 entry->error = PCICFG_SUCCESS; in pcicfg_bridge_assign()
1891 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
1907 entry->io_last; in pcicfg_bridge_assign()
1911 entry->memory_last; in pcicfg_bridge_assign()
1924 "bus-range", bus_range, 2) != DDI_SUCCESS) { in pcicfg_bridge_assign()
1925 DEBUG0("Failed to set bus-range property"); in pcicfg_bridge_assign()
1926 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
1930 if (entry->io_len > 0) { in pcicfg_bridge_assign()
1931 range[0].size_lo = entry->io_last - entry->io_base; in pcicfg_bridge_assign()
1934 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
1938 if (entry->memory_len > 0) { in pcicfg_bridge_assign()
1940 entry->memory_last - entry->memory_base; in pcicfg_bridge_assign()
1943 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
1972 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
1990 DEBUG2("REGISTER off %x (64)LO ----> [0x%x]\n", in pcicfg_bridge_assign()
1993 DEBUG2("REGISTER off %x (64)HI ----> [0x%x]\n", in pcicfg_bridge_assign()
2011 DEBUG2("REGISTER off %x(32)LO ----> [0x%x]\n", in pcicfg_bridge_assign()
2025 DEBUG2("REGISTER off %x (I/O)LO ----> [0x%x]\n", in pcicfg_bridge_assign()
2036 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
2048 entry->error = PCICFG_FAILURE; in pcicfg_bridge_assign()
2255 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_device_assign_readonly()
2257 DEBUG0("Failed to read assigned-addresses property\n"); in pcicfg_device_assign_readonly()
2272 * For each "assigned-addresses" property entry with a length, in pcicfg_device_assign_readonly()
2377 * This should not find an existing entry - so in pcicfg_allocate_chunk()
2383 mem_request = &phdl->mem_req; in pcicfg_allocate_chunk()
2384 io_request = &phdl->io_req; in pcicfg_allocate_chunk()
2387 * From this point in the tree - walk the devices, in pcicfg_allocate_chunk()
2396 if (phdl->error != PCICFG_SUCCESS) { in pcicfg_allocate_chunk()
2398 return (phdl->error); in pcicfg_allocate_chunk()
2406 mem_request->ra_len); in pcicfg_allocate_chunk()
2408 io_request->ra_len); in pcicfg_allocate_chunk()
2410 mem_request->ra_align_mask = in pcicfg_allocate_chunk()
2411 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ in pcicfg_allocate_chunk()
2412 io_request->ra_align_mask = in pcicfg_allocate_chunk()
2413 PCICFG_IOGRAN - 1; /* 4K alignment on I/O space */ in pcicfg_allocate_chunk()
2414 io_request->ra_boundbase = 0; in pcicfg_allocate_chunk()
2415 io_request->ra_boundlen = PCICFG_4GIG_LIMIT; in pcicfg_allocate_chunk()
2416 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; in pcicfg_allocate_chunk()
2418 mem_request->ra_len = in pcicfg_allocate_chunk()
2419 PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN); in pcicfg_allocate_chunk()
2421 io_request->ra_len = in pcicfg_allocate_chunk()
2422 PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN); in pcicfg_allocate_chunk()
2431 phdl->memory_base = phdl->memory_last = mem_answer; in pcicfg_allocate_chunk()
2432 phdl->memory_len = alen; in pcicfg_allocate_chunk()
2434 phdl->mem_hole.start = phdl->memory_base; in pcicfg_allocate_chunk()
2435 phdl->mem_hole.len = phdl->memory_len; in pcicfg_allocate_chunk()
2436 phdl->mem_hole.next = (hole_t *)NULL; in pcicfg_allocate_chunk()
2444 phdl->memory_len = phdl->io_len = 0; in pcicfg_allocate_chunk()
2448 phdl->io_base = phdl->io_last = (uint32_t)io_answer; in pcicfg_allocate_chunk()
2449 phdl->io_len = (uint32_t)alen; in pcicfg_allocate_chunk()
2451 phdl->io_hole.start = phdl->io_base; in pcicfg_allocate_chunk()
2452 phdl->io_hole.len = phdl->io_len; in pcicfg_allocate_chunk()
2453 phdl->io_hole.next = (hole_t *)NULL; in pcicfg_allocate_chunk()
2456 phdl->memory_base, phdl->memory_len); in pcicfg_allocate_chunk()
2458 phdl->io_base, phdl->io_len); in pcicfg_allocate_chunk()
2475 len += hole->len; in pcicfg_unused_space()
2476 hole = hole->next; in pcicfg_unused_space()
2492 hole_t *nhole, *hole = addr_hole->next; in pcicfg_free_hole()
2495 nhole = hole->next; in pcicfg_free_hole()
2508 actual_hole_start = PCICFG_ROUND_UP(hole->start, length); in pcicfg_alloc_hole()
2509 if (((actual_hole_start - hole->start) + length) <= hole->len) { in pcicfg_alloc_hole()
2511 hole->start, hole->len, length); in pcicfg_alloc_hole()
2512 ostart = hole->start; in pcicfg_alloc_hole()
2513 olen = hole->len; in pcicfg_alloc_hole()
2515 if ((actual_hole_start - hole->start) == 0) { in pcicfg_alloc_hole()
2516 hole->start += length; in pcicfg_alloc_hole()
2517 hole->len -= length; in pcicfg_alloc_hole()
2518 if (hole->start > *alast) in pcicfg_alloc_hole()
2519 *alast = hole->start; in pcicfg_alloc_hole()
2521 hole->len = actual_hole_start - hole->start; in pcicfg_alloc_hole()
2524 nhole->start = actual_hole_start + length; in pcicfg_alloc_hole()
2525 nhole->len = (ostart + olen) - nhole->start; in pcicfg_alloc_hole()
2526 nhole->next = NULL; in pcicfg_alloc_hole()
2527 thole = hole->next; in pcicfg_alloc_hole()
2528 hole->next = nhole; in pcicfg_alloc_hole()
2529 nhole->next = thole; in pcicfg_alloc_hole()
2530 if (nhole->start > *alast) in pcicfg_alloc_hole()
2531 *alast = nhole->start; in pcicfg_alloc_hole()
2533 nhole->start, nhole->len); in pcicfg_alloc_hole()
2536 hole->start, hole->len); in pcicfg_alloc_hole()
2540 hole = hole->next; in pcicfg_alloc_hole()
2553 new_mem = pcicfg_alloc_hole(&entry->mem_hole, &entry->memory_last, in pcicfg_get_mem()
2555 if (new_mem) { /* if non-zero, found a hole. */ in pcicfg_get_mem()
2560 length, ddi_get_name(entry->dip)); in pcicfg_get_mem()
2573 io_last = entry->io_last; in pcicfg_get_io()
2574 new_io = (uint32_t)pcicfg_alloc_hole(&entry->io_hole, &io_last, length); in pcicfg_get_io()
2575 if (new_io) { /* if non-zero, found a hole. */ in pcicfg_get_io()
2576 entry->io_last = (uint32_t)io_last; in pcicfg_get_io()
2581 length, ddi_get_name(entry->dip)); in pcicfg_get_io()
2597 entry->error = PCICFG_SUCCESS; in pcicfg_sum_resources()
2599 mem_request = &entry->mem_req; in pcicfg_sum_resources()
2600 io_request = &entry->io_req; in pcicfg_sum_resources()
2604 entry->error = PCICFG_FAILURE; in pcicfg_sum_resources()
2611 * If its a bridge - just record the highest bus seen in pcicfg_sum_resources()
2615 if (entry->highest_bus < pci_config_get8(handle, in pcicfg_sum_resources()
2617 entry->highest_bus = in pcicfg_sum_resources()
2622 entry->error = PCICFG_FAILURE; in pcicfg_sum_resources()
2633 entry->memory_len = 0; in pcicfg_sum_resources()
2634 entry->io_len = 0; in pcicfg_sum_resources()
2635 entry->error = PCICFG_FAILURE; in pcicfg_sum_resources()
2649 mem_request->ra_len = in pcicfg_sum_resources()
2651 PCICFG_ROUND_UP(mem_request->ra_len, in pcicfg_sum_resources()
2653 DEBUG1("ADDING 32 --->0x%x\n", in pcicfg_sum_resources()
2658 mem_request->ra_len = in pcicfg_sum_resources()
2660 PCICFG_ROUND_UP(mem_request->ra_len, in pcicfg_sum_resources()
2662 DEBUG1("ADDING 64 --->0x%x\n", in pcicfg_sum_resources()
2667 io_request->ra_len = in pcicfg_sum_resources()
2669 PCICFG_ROUND_UP(io_request->ra_len, in pcicfg_sum_resources()
2671 DEBUG1("ADDING I/O --->0x%x\n", in pcicfg_sum_resources()
2675 /* Config space register - not included */ in pcicfg_sum_resources()
2705 entry_p->error = PCICFG_SUCCESS; in pcicfg_find_resource_end()
2707 if (dip == entry_p->dip) { in pcicfg_find_resource_end()
2730 base = entry_p->memory_base; in pcicfg_find_resource_end()
2731 entry_p->memory_base = MAX(base, lo + size); in pcicfg_find_resource_end()
2734 base = entry_p->memory_base; in pcicfg_find_resource_end()
2735 entry_p->memory_base = MAX(base, in pcicfg_find_resource_end()
2739 base = entry_p->io_base; in pcicfg_find_resource_end()
2740 entry_p->io_base = MAX(base, lo + size); in pcicfg_find_resource_end()
2749 DDI_PROP_DONTPASS, "assigned-addresses", in pcicfg_find_resource_end()
2751 DEBUG0("Node doesn't have assigned-addresses\n"); in pcicfg_find_resource_end()
2764 entry_p->memory_base) { in pcicfg_find_resource_end()
2765 entry_p->memory_base = in pcicfg_find_resource_end()
2774 entry_p->memory_base) { in pcicfg_find_resource_end()
2775 entry_p->memory_base = PCICFG_LADDR( in pcicfg_find_resource_end()
2784 entry_p->io_base) { in pcicfg_find_resource_end()
2785 entry_p->io_base = in pcicfg_find_resource_end()
2823 * assigned-addresses but for now it is better to in pcicfg_free_bridge_resources()
2884 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, in pcicfg_free_bridge_resources()
2886 DEBUG0("Failed to read bus-range property\n"); in pcicfg_free_bridge_resources()
2891 bus[0], bus[1] - bus[0] + 1); in pcicfg_free_bridge_resources()
2894 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), in pcicfg_free_bridge_resources()
2917 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_free_device_resources()
2919 DEBUG0("Failed to read assigned-addresses property\n"); in pcicfg_free_device_resources()
2924 * For each "assigned-addresses" property entry with a length, in pcicfg_free_device_resources()
2940 DEBUG1("pcicfg_free_device_resources - Trouble freeing " in pcicfg_free_device_resources()
2999 for (ptr = &pcicfg_class_lookup[0]; ptr->name != NULL; ptr++) { in pcicfg_get_class_name()
3000 if (ptr->class_code == classcode) { in pcicfg_get_class_name()
3001 return (ptr->name); in pcicfg_get_class_name()
3036 ctrl->dip = NULL; in pcicfg_match_dev()
3041 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); in pcicfg_match_dev()
3042 pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); in pcicfg_match_dev()
3050 if ((pci_dev == ctrl->device) && (pci_func == ctrl->function)) { in pcicfg_match_dev()
3052 ctrl->dip = dip; in pcicfg_match_dev()
3072 "assigned-addresses", (caddr_t)&assigned, &alen); in pcicfg_update_assigned_prop()
3077 DEBUG0("no memory for assigned-addresses property\n"); in pcicfg_update_assigned_prop()
3081 "assigned-addresses", (int *)newone, in pcicfg_update_assigned_prop()
3091 * assigned-addresses(s) plus one and then in pcicfg_update_assigned_prop()
3101 * Write out the new "assigned-addresses" spec in pcicfg_update_assigned_prop()
3104 "assigned-addresses", (int *)newreg, in pcicfg_update_assigned_prop()
3137 DEBUG0("no ranges property - creating one\n"); in pcicfg_update_ranges_prop()
3206 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), in pcicfg_update_reg_prop()
3207 PCI_REG_DEV_G(reg->pci_phys_hi), in pcicfg_update_reg_prop()
3208 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_reg_prop()
3257 DEBUG2("pcicfg_update_available_prop() - Address %lx Size %x\n", in pcicfg_update_available_prop()
3258 newone->pci_phys_low, newone->pci_size_low); in pcicfg_update_available_prop()
3330 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), in pcicfg_update_assigned_prop_value()
3331 PCI_REG_DEV_G(reg->pci_phys_hi), in pcicfg_update_assigned_prop_value()
3332 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); in pcicfg_update_assigned_prop_value()
3380 * fast back-to-back, and addr. stepping? in pcicfg_device_on()
3408 /* These two exists only for non-bridges */ in pcicfg_set_standard_props()
3413 "min-grant", byteval)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3419 "max-latency", byteval)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3431 "vendor-id", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3436 "device-id", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3441 "revision-id", byteval)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3449 "class-code", wordval)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3452 /* devsel-speed starts at the 9th bit */ in pcicfg_set_standard_props()
3456 "devsel-speed", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3463 * is set, non-existent otherwise in pcicfg_set_standard_props()
3469 "fast-back-to-back", 0)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3477 "66mhz-capable", 0)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3483 "udf-supported", 0)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3491 * is non-zero then the property exists with the value in pcicfg_set_standard_props()
3497 "subsystem-vendor-id", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3504 "subsystem-id", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3511 "cache-line-size", val)) != DDI_SUCCESS) { in pcicfg_set_standard_props()
3517 * If the Interrupt Pin register is non-zero then the in pcicfg_set_standard_props()
3522 * If interrupt pin is non-zero, in pcicfg_set_standard_props()
3543 dip, "physical-slot#", wordval)) in pcicfg_set_standard_props()
3568 "#address-cells", 3)) != DDI_SUCCESS) { in pcicfg_set_busnode_props()
3572 "#size-cells", 2)) != DDI_SUCCESS) { in pcicfg_set_busnode_props()
3577 * Create primary-bus and secondary-bus properties to be used in pcicfg_set_busnode_props()
3580 if (pbus != -1 && sbus != -1) { in pcicfg_set_busnode_props()
3582 "primary-bus", pbus)) != DDI_SUCCESS) { in pcicfg_set_busnode_props()
3586 "secondary-bus", sbus)) != DDI_SUCCESS) { in pcicfg_set_busnode_props()
3599 char *name; in pcicfg_set_childnode_props() local
3608 /* set the property prefix based on the device type */ in pcicfg_set_childnode_props()
3624 * NOTE: These are for both a child and PCI-PCI bridge node in pcicfg_set_childnode_props()
3628 * "name" property rule in pcicfg_set_childnode_props()
3629 * -------------------- in pcicfg_set_childnode_props()
3636 * |------------|-----------------------|-----------------------| in pcicfg_set_childnode_props()
3640 * |------------|-----------------------|-----------------------| in pcicfg_set_childnode_props()
3644 * |------------|-----------------------|-----------------------| in pcicfg_set_childnode_props()
3661 * not the convention. In those cases use the name as created in pcicfg_set_childnode_props()
3663 * is a generic name first. in pcicfg_set_childnode_props()
3666 name = buffer; in pcicfg_set_childnode_props()
3668 if ((name = pcicfg_get_class_name(classcode)) == NULL) { in pcicfg_set_childnode_props()
3670 * Set name to the above fabricated name in pcicfg_set_childnode_props()
3672 name = buffer; in pcicfg_set_childnode_props()
3677 * The node name field needs to be filled in with the name in pcicfg_set_childnode_props()
3679 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { in pcicfg_set_childnode_props()
3696 * pciSSSS.ssss -> not created for PCIe as per PCIe bindings in pcicfg_set_childnode_props()
3715 /* pciSSSS.ssss -> not created for PCIe as per PCIe bindings */ in pcicfg_set_childnode_props()
3762 DEBUG1("pcicfg_set_childnode_props - creating name=%s\n", name); in pcicfg_set_childnode_props()
3764 "name", name)) != DDI_SUCCESS) { in pcicfg_set_childnode_props()
3766 DEBUG0("pcicfg_set_childnode_props - Unable to create name " in pcicfg_set_childnode_props()
3783 DEBUG3("Setting bridge bus-range %d,%d,%d\n", primary, secondary, in pcicfg_set_bus_numbers()
3811 * The highest bus seen during probing is the max-subordinate bus in pcicfg_setup_bridge()
3813 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); in pcicfg_setup_bridge()
3825 DDI_PROP_DONTPASS, "primary-bus", -1); in pcicfg_setup_bridge()
3827 DDI_PROP_DONTPASS, "secondary-bus", -1); in pcicfg_setup_bridge()
3828 if (pbus != -1 && sbus != -1) { in pcicfg_setup_bridge()
3855 PCICFG_HIWORD(PCICFG_LOADDR(entry->memory_last))); in pcicfg_setup_bridge()
3861 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(entry->io_last)))); in pcicfg_setup_bridge()
3863 PCICFG_HIWORD(PCICFG_LOADDR(entry->io_last))); in pcicfg_setup_bridge()
3902 PCICFG_ROUND_DOWN(entry->memory_last, in pcicfg_update_bridge()
3907 PCICFG_ROUND_DOWN(entry->memory_last, in pcicfg_update_bridge()
3914 if ((length = (PCICFG_ROUND_UP(entry->memory_last, in pcicfg_update_bridge()
3915 PCICFG_MEMGRAN) - entry->memory_last)) > 0) { in pcicfg_update_bridge()
3926 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, in pcicfg_update_bridge()
3930 PCICFG_HIWORD(PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, in pcicfg_update_bridge()
3939 if ((length = (PCICFG_ROUND_UP(entry->io_last, in pcicfg_update_bridge()
3940 PCICFG_IOGRAN) - entry->io_last)) > 0) { in pcicfg_update_bridge()
3955 regs->cmd = val = pci_config_get16(h, PCI_CONF_COMM); in pcicfg_disable_bridge_probe_err()
3958 regs->bcntl = val = pci_config_get16(h, PCI_BCNF_BCNTRL); in pcicfg_disable_bridge_probe_err()
3967 if (regs->pcie_dev) { in pcicfg_disable_bridge_probe_err()
3975 regs->pcie_cap_off = cap_ptr; in pcicfg_disable_bridge_probe_err()
3976 regs->devctl = devctl = PCI_CAP_GET16(h, 0, cap_ptr, in pcicfg_disable_bridge_probe_err()
3998 if (regs->pcie_dev) { in pcicfg_enable_bridge_probe_err()
4000 pci_config_put16(h, regs->pcie_cap_off + PCIE_DEVCTL, in pcicfg_enable_bridge_probe_err()
4001 regs->devctl); in pcicfg_enable_bridge_probe_err()
4004 pci_config_put16(h, PCI_BCNF_BCNTRL, regs->bcntl); in pcicfg_enable_bridge_probe_err()
4005 pci_config_put16(h, PCI_CONF_COMM, regs->cmd); in pcicfg_enable_bridge_probe_err()
4081 * Child node properties NOTE: Both for PCI-PCI bridge and child node in pcicfg_probe_children()
4091 * If this is not a multi-function card only probe function zero. in pcicfg_probe_children()
4100 DEBUG1("---Vendor ID = [0x%x]\n", in pcicfg_probe_children()
4102 DEBUG1("---Device ID = [0x%x]\n", in pcicfg_probe_children()
4112 DEBUG3("--Bridge found bus [0x%x] device" in pcicfg_probe_children()
4115 /* Only support read-only probe for leaf device */ in pcicfg_probe_children()
4127 DEBUG3("--Leaf device found bus [0x%x] device" in pcicfg_probe_children()
4133 * with read-only probe, don't do any resource in pcicfg_probe_children()
4142 * for readonly probe "assigned-addresses" property in pcicfg_probe_children()
4420 * Child node properties NOTE: Both for PCI-PCI bridge and child node in pcicfg_fcode_probe()
4431 * If this is not a multi-function card only probe function zero. in pcicfg_fcode_probe()
4442 * XXX - Transparent bridges are handled differently in pcicfg_fcode_probe()
4446 * or call the fcode interpreter to try to load a drop-in. in pcicfg_fcode_probe()
4451 DEBUG3("--Bridge found bus [0x%x] device" in pcicfg_fcode_probe()
4454 /* Only support read-only probe for leaf device */ in pcicfg_fcode_probe()
4464 DEBUG3("--Leaf device found bus [0x%x] device" in pcicfg_fcode_probe()
4474 /* XXX for now, don't run Fcode in read-only probe. */ in pcicfg_fcode_probe()
4508 * Add resource to assigned-addresses. in pcicfg_fcode_probe()
4542 * Create the fcode-rom-offset property. The in pcicfg_fcode_probe()
4547 new_child, "fcode-rom-offset", 0) in pcicfg_fcode_probe()
4550 "fcode-rom-offset property\n"); in pcicfg_fcode_probe()
4583 DEBUG3("Before int DIP=%lx binding name %s major %d\n", in pcicfg_fcode_probe()
4589 DEBUG1("returned from fcode_interpreter() - " in pcicfg_fcode_probe()
4616 DEBUG3("DIP=%lx binding name %s major %d\n", new_child, in pcicfg_fcode_probe()
4691 DEBUG0("No Drop-in Probe device ourself\n"); in pcicfg_fcode_probe()
4824 * Add to "assigned-addresses" property in pcicfg_populate_props_from_bar()
4880 * Add to "assigned-addresses" property in pcicfg_populate_props_from_bar()
4961 DEBUG0("Can not setup resource map - NDI_RA_TYPE_PCI_BUSNUM\n"); in pcicfg_probe_bridge()
4970 (void) ndi_ra_free(new_child, pcibus_base+1, pcibus_alen-1, in pcicfg_probe_bridge()
4974 max_bus = pcibus_base + pcibus_alen - 1; in pcicfg_probe_bridge()
4978 DEBUG1("NEW bus found ->[%d]\n", new_bus); in pcicfg_probe_bridge()
4996 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ in pcicfg_probe_bridge()
5018 DEBUG0("Can not setup resource map - NDI_RA_TYPE_MEM\n"); in pcicfg_probe_bridge()
5034 req.ra_align_mask = PCICFG_IOGRAN - 1; /* 4k alignment */ in pcicfg_probe_bridge()
5061 DEBUG0("Can not setup resource map - NDI_RA_TYPE_IO\n"); in pcicfg_probe_bridge()
5076 * Setup "bus-range" property before onlining the bridge. in pcicfg_probe_bridge()
5082 "bus-range", bus_range, 2) != DDI_SUCCESS) { in pcicfg_probe_bridge()
5083 DEBUG0("Failed to set bus-range property"); in pcicfg_probe_bridge()
5112 PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) - 1))); in pcicfg_probe_bridge()
5125 req.ra_len = (mem_answer + mem_alen) - in pcicfg_probe_bridge()
5149 PCICFG_IOGRAN)))) - 1); in pcicfg_probe_bridge()
5154 - 1); in pcicfg_probe_bridge()
5167 req.ra_len = (io_answer + io_alen) - in pcicfg_probe_bridge()
5249 DEBUG0("Bridge Programming Complete - probe children\n"); in pcicfg_probe_bridge()
5302 "ari-enabled", NULL, 0); in pcicfg_probe_bridge()
5375 * here otherwise it will be out-of-sync with the actual free in pcicfg_probe_bridge()
5432 mem_size = mem_end - mem_assigned; in pcicfg_probe_bridge()
5433 io_size = io_end - io_assigned; in pcicfg_probe_bridge()
5462 mem_end, (mem_answer + mem_alen) - mem_end, NDI_RA_TYPE_MEM, in pcicfg_probe_bridge()
5481 PCICFG_HIWORD(mem_end) - 1); in pcicfg_probe_bridge()
5482 mem_size = mem_end - mem_base; in pcicfg_probe_bridge()
5489 io_end, (io_answer + io_alen) - io_end, in pcicfg_probe_bridge()
5512 PCICFG_LOADDR(io_end) - 1))); in pcicfg_probe_bridge()
5515 PCICFG_HIWORD(PCICFG_LOADDR(io_end - 1))); in pcicfg_probe_bridge()
5517 io_size = io_end - io_base; in pcicfg_probe_bridge()
5520 if ((max_bus - *highest_bus) > 0) { in pcicfg_probe_bridge()
5525 *highest_bus+1, max_bus - *highest_bus, in pcicfg_probe_bridge()
5540 "bus-range", bus_range, 2) != DDI_SUCCESS) { in pcicfg_probe_bridge()
5541 DEBUG0("Failed to set bus-range property"); in pcicfg_probe_bridge()
5551 DEBUG2("Creating Ranges property - Mem Address %lx Mem Size %x\n", in pcicfg_probe_bridge()
5553 DEBUG2(" - I/O Address %lx I/O Size %x\n", in pcicfg_probe_bridge()
5585 * failure other than map itself being non-existent. So we are Ok. in pcicfg_probe_bridge()
5589 DEBUG0("Can not destroy resource map - NDI_RA_TYPE_MEM\n"); in pcicfg_probe_bridge()
5594 DEBUG0("Can not destroy resource map - NDI_RA_TYPE_IO\n"); in pcicfg_probe_bridge()
5600 DEBUG0("Can't destroy resource map - NDI_RA_TYPE_PCI_BUSNUM\n"); in pcicfg_probe_bridge()
5685 if (tmp == -1) { in pcicfg_config_setup()
5689 /* XXX - Need to check why HV is returning 0 */ in pcicfg_config_setup()
5766 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)®, in pcicfg_dump_assigned()
5768 DEBUG0("Failed to read assigned-addresses property\n"); in pcicfg_dump_assigned()
5774 DEBUG4("pcicfg_dump_assigned - size=%x low=%x mid=%x high=%x\n", in pcicfg_dump_assigned()
5807 DEBUG4("pcicfg_load_fcode() - " in pcicfg_load_fcode()
5810 DEBUG2("pcicfg_load_fcode() - vendor_id=%x device_id=%x\n", in pcicfg_load_fcode()
5844 DEBUG2("ROM 0x%x --> 0x%x\n", i, in pcicfg_load_fcode()
5851 * for non-21554 devices use peek so we don't panic due to in pcicfg_load_fcode()
5928 DEBUG0("ROM is of x86/PC-AT Type\n"); in pcicfg_load_fcode()
6008 * exit from this function, "assigned-addresses" are created in pcicfg_fcode_assign_bars()
6019 DEBUG1("pcicfg_fcode_assign_bars :%s\n", DEVI(dip)->devi_name); in pcicfg_fcode_assign_bars()
6066 * - allocates address space in pcicfg_fcode_assign_bars()
6067 * - programs the BAR in pcicfg_fcode_assign_bars()
6068 * - adds an "assigned-addresses" property in pcicfg_fcode_assign_bars()
6073 size, DEVI(dip)->devi_name, i); in pcicfg_fcode_assign_bars()
6111 size, DEVI(dip)->devi_name); in pcicfg_fcode_assign_bars()
6126 * Add resource to assigned-addresses. in pcicfg_fcode_assign_bars()
6140 " assigned-address property for dev %s\n", in pcicfg_fcode_assign_bars()
6141 DEVI(dip)->devi_name); in pcicfg_fcode_assign_bars()
6153 * We came in with no "assigned-addresses". in pcicfg_fcode_assign_bars()
6172 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_free_all_resources()
6174 DEBUG0("Failed to read assigned-addresses property\n"); in pcicfg_free_all_resources()
6219 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_alloc_new_resources()
6226 DEBUG1("assigned-addresses property len=%x\n", acount); in pcicfg_alloc_new_resources()
6230 * assigned-addresses property. If it does not exist, allocate in pcicfg_alloc_new_resources()
6243 "- %x - MATCH\n", in pcicfg_alloc_new_resources()
6252 " - %x - RESIZE" in pcicfg_alloc_new_resources()
6265 " - %x - ENOUGH" in pcicfg_alloc_new_resources()
6283 "- PARTIAL MATCH assigned 0x%x " in pcicfg_alloc_new_resources()
6294 " SS bits of - 0x%x -" in pcicfg_alloc_new_resources()
6296 DEVI(dip)->devi_name); in pcicfg_alloc_new_resources()
6316 * We are allocating resources for one of three reasons - in pcicfg_alloc_new_resources()
6317 * - Fcode wants a larger address space in pcicfg_alloc_new_resources()
6318 * - Fcode has set changed/set n, p, t bits. in pcicfg_alloc_new_resources()
6319 * - It is a new "reg", it should be only ROM bar, but in pcicfg_alloc_new_resources()
6366 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, in pcicfg_alloc_resource()
6368 DEBUG0("pcicfg_alloc_resource - " in pcicfg_alloc_resource()
6369 "searching assigned-addresses\n"); in pcicfg_alloc_resource()
6374 * Walk through the assigned-addresses entries. If there is in pcicfg_alloc_resource()
6379 DEBUG1("pcicfg_alloc_resource - MATCH %x\n", in pcicfg_alloc_resource()
6543 DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi); in pcicfg_alloc_resource()
6651 DEBUG1("updating assigned-addresss for %x\n", phys_spec.pci_phys_hi); in pcicfg_free_resource()
6671 "assigned-addresses", (caddr_t)&assigned, &alen); in pcicfg_remove_assigned_prop()
6676 DEBUG0("no memory for assigned-addresses property\n"); in pcicfg_remove_assigned_prop()
6679 DEBUG0("assigned-addresses property does not exist\n"); in pcicfg_remove_assigned_prop()
6684 * Make a copy of old assigned-addresses property. in pcicfg_remove_assigned_prop()
6689 status = ndi_prop_remove(DDI_DEV_T_NONE, dip, "assigned-addresses"); in pcicfg_remove_assigned_prop()
6693 * If "assigned-addresses" is retrieved from PROM, the in pcicfg_remove_assigned_prop()
6697 oldone->pci_phys_hi); in pcicfg_remove_assigned_prop()
6711 * Rebuild the assigned-addresses property. in pcicfg_remove_assigned_prop()
6714 if (assigned_copy[i].pci_phys_hi != oldone->pci_phys_hi) { in pcicfg_remove_assigned_prop()
6721 * Free the copy of the original assigned-addresses. in pcicfg_remove_assigned_prop()
6744 hp->ah_vers = VERS_ACCHDL; in pcicfg_map_phys()
6745 hp->ah_dip = dip; in pcicfg_map_phys()
6746 hp->ah_rnumber = 0; in pcicfg_map_phys()
6747 hp->ah_offset = 0; in pcicfg_map_phys()
6748 hp->ah_len = 0; in pcicfg_map_phys()
6749 hp->ah_acc = *accattrp; in pcicfg_map_phys()
6765 hp->ah_addr = *addrp; in pcicfg_map_phys()
6788 (void) ddi_map(hp->ah_dip, &mr, hp->ah_offset, in pcicfg_unmap_phys()
6789 hp->ah_len, &hp->ah_addr); in pcicfg_unmap_phys()