Lines Matching defs:bmac
659 struct bmac { struct
660 uint32_t txrst; /* 0x6000 tx software reset (RW) */
661 uint32_t rxrst; /* 0x6004 rx software reset Reg (RW) */
662 uint32_t spcmd; /* 0x6008 Send Pause Command Reg (RW) */
663 uint32_t res1; /* 0x600C reserved */
664 uint32_t txsts; /* 0x6010 tx MAC status reg (R-AC) */
665 uint32_t rxsts; /* 0x6014 rx MAC status reg (R-AC) */
666 uint32_t macctl_sts; /* 0x6018 MAC Control Stat Reg (R-AC) */
667 uint32_t res2; /* 0x601C reserved */
668 uint32_t txmask; /* 0x6020 tx MAC Mask Register (RW) */
669 uint32_t rxmask; /* 0x6024 rx MAC Mask register (RW) */
670 uint32_t macctl_mask; /* 0x6028 MAC Control Mask Reg (RW) */
671 uint32_t res3; /* 0x602C reserved */
672 uint32_t txcfg; /* 0x6030 tx config reg [8-0] (RW) */
673 uint32_t rxcfg; /* 0x6034 rx config reg [7-0] (RW) */
674 uint32_t macctl_cfg; /* 0x6038 MAC Control Config Reg (RW) */
675 uint32_t xifc; /* 0x603C XIF Config. reg [7-0] (RW) */
676 uint32_t ipg0; /* 0x6040 Inter pkt Gap 0 [7-0] (RW) */
677 uint32_t ipg1; /* 0x6044 Inter pkt Gap 1 [7-0] (RW) */
678 uint32_t ipg2; /* 0x6048 Inter pkt Gap 2 [7-0] (RW) */
679 uint32_t slot; /* 0x604C slot time reg [7-0] (RW) */
680 uint32_t macmin; /* 0x6050 MAC min frame sze [9-0](RW) */
681 uint32_t macmax; /* 0x6054 MAC max pkt sze [14-0] (RW) */
682 uint32_t palen; /* 0x6058 preamble len reg [9-0] (RW) */
683 uint32_t jam; /* 0x605C jam size reg [3-0] (RW) */
684 uint32_t alimit; /* 0x6060 attempt limit reg [7-0](RW) */
685 uint32_t macctl_type; /* 0x6064 MAC Control Type Reg (RW) */
686 uint32_t res4[6]; /* reserved 0x6068 - 0x607C */
687 uint32_t madd0; /* 0x6080 Norm MAC adrs 0 [15-0] (RW) */
688 uint32_t madd1; /* 0x6084 Norm MAC adrs 1 [31-16](RW) */
689 uint32_t madd2; /* 0x6088 Norm MAC adrs 2 [47-32](RW) */
690 uint32_t madd3; /* 0x608C Alt. MAC adrs 0 [15-0](RW) */
691 uint32_t madd4; /* 0x6090 Alt. MAC adrs 1 [31-16](RW) */
692 uint32_t madd5; /* 0x6094 Alt. MAC adrs 2 [47-32](RW) */
693 uint32_t madd6; /* 0x6098 Control MAC adrs 0 [15-0](RW) */
694 uint32_t madd7; /* 0x609C Control MAC adrs 1 [31-16](RW) */
695 uint32_t madd8; /* 0x60A0 Control MAC adrs 2 [47-32](RW) */
696 uint32_t afr0; /* 0x60A4 addr filt reg 0_0 [15-0](RW) */
697 uint32_t afr1; /* 0x60A8 addr filt reg 0_1 [15-0](RW) */
698 uint32_t afr2; /* 0x60AC addr filt reg 0_2 [15-0](RW) */
699 uint32_t afmr1_2; /* 0x60B0 addr filt msk reg 1,2 [8-0](RW) */
700 uint32_t afmr0; /* 0x60B4 addr filt msk reg 0 [15-0](RW) */
701 uint32_t res5[2]; /* 0x60B8 - 0x60BC Reserved */
702 uint32_t hash0; /* 0x60C0 h-table 0 [15-0] (RW) */
703 uint32_t hash1; /* 0x60C4 h-table 1 [31-16] (RW) */
704 uint32_t hash2; /* 0x60C8 h-table 2 [47-32] (RW) */
705 uint32_t hash3; /* 0x60CC h-table 3 [63-48] (RW) */
706 uint32_t hash4; /* 0x60D0 h-table 4 [79-64] (RW) */
707 uint32_t hash5; /* 0x60D4 h-table 5 [95-80] (RW) */
708 uint32_t hash6; /* 0x60D8 h-table 6 [111-96] (RW) */
709 uint32_t hash7; /* 0x60DC h-table 7 [127-112] (RW) */
710 uint32_t hash8; /* 0x60E0 h-table 8 [143-128] (RW) */
711 uint32_t hash9; /* 0x60E4 h-table 9 [159-144] (RW) */
712 uint32_t hash10; /* 0x60E8 h-table 10 [175-160] (RW) */
713 uint32_t hash11; /* 0x60EC h-table 11 [191-176] (RW) */
714 uint32_t hash12; /* 0x60F0 h-table 12 [207-192] (RW) */
715 uint32_t hash13; /* 0x60F4 h-table 13 [223-208] (RW) */
716 uint32_t hash14; /* 0x60F8 h-table 14 [239-224] (RW) */
717 uint32_t hash15; /* 0x60FC h-table 15 [255-240] (RW) */
718 uint32_t nccnt; /* 0x6100 normal coll cnt [15-0] (RW) */
719 uint32_t fccnt; /* 0x6104 1st succes coll [15-0] (RW) */
720 uint32_t excnt; /* 0x6108 excess coll cnt[15-0] (RW) */
721 uint32_t ltcnt; /* 0x610C late coll cnt [15-0] (RW) */
722 uint32_t dcnt; /* 0x6110 defer timer cnt [15-0] (RW) */
723 uint32_t pattempts; /* 0x6114 peak attempt reg [7-0] (RW) */
724 uint32_t frcnt; /* 0x6118 rcv frame cnt [15-0] (RW) */
725 uint32_t lecnt; /* 0x611C rx len err cnt [15-0] (RW) */
726 uint32_t aecnt; /* 0x6120 rx align err cnt[15-0] (RW) */
727 uint32_t fecnt; /* 0x6124 rcv crc err cnt [15-0] (RW) */
728 uint32_t rxcv; /* 0x6128 rx code viol reg [15-0](RW) */
729 uint32_t res6; /* 0x612C Reserved */
730 uint32_t rseed; /* 0x6130 random num seed [9-0] (RW) */
731 uint32_t macsm; /* 0x6134 MAC state mach reg [7-0](R) */