Lines Matching +full:trigger +full:- +full:address
54 #define Adr %l5 /* data address pointer */
57 #define TRIGGER 0x33 macro
59 save %sp, -SA(MINFRAME), %sp
74 tst Tmp2 ! non-zero?
101 ! read/write/format data-xfer case - they have a result phase
106 ! XXX- test for null raddr
138 ! END OF TRANSFER - if read/write, toggle the TC
188 ! recalibrate/seek - no result phase, must do sense interrupt status.
211 ! fdc->c_csb.csb_rslt[0] = *fifo;
220 ! fdc->c_csb.csb_rslt[1] = *fifo;
232 add Fdc, FD_RSLT, Adr ! load address of csb->csb_rslt
252 add Adr, 1, Adr ! increment address
271 ! at this time. Wait to trigger it at the end of the handler
274 mov TRIGGER, Tmp2
280 ! impl_setintreg uses %l4-%l7
317 cmp Tmp2, TRIGGER