Lines Matching refs:g3
652 ldstub [%o0 + SFMMU_CTX_LOCK], %g3 ! %g3 = per process (PP) lock
654 brz %g3, 5f
657 brnz,a,pt %g3, 4b ! spin if lock is 1
658 ldub [%o0 + SFMMU_CTX_LOCK], %g3
660 ldstub [%o0 + SFMMU_CTX_LOCK], %g3 ! %g3 = PP lock
705 add %o3, MMU_CTX_CNUM, %g3
719 ld [%g3], %o1
735 ! %g3 = addr of mmu_ctxp->cnum
737 cas [%g3], %o1, %o5
740 ld [%g3], %o1
800 ldx [%o2], %g3 /* current */
804 cmp %g2, %g3 /* is modified = current? */
806 stx %g3, [%o0] /* update new original */
811 ldx [%o2], %g3 /* new current */
812 stx %g3, [%o0] /* save as new original */
814 mov %g3, %g1
821 ldx [%o2], %g3 /* current */
823 cmp %g3, %g2 /* is modified = current? */
1358 SETUP_TSB_ASI(%o3, %g3)
1454 TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
1583 mov T_INSTR_MMU_MISS, %g3
1586 mov T_INSTR_MMU_MISS, %g3
1588 mov T_DATA_PROT, %g3 /* arg2 = traptype */
1590 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1592 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1624 mov T_INSTR_MMU_MISS, %g3
1627 mov T_INSTR_MMU_MISS, %g3
1629 mov T_DATA_PROT, %g3 /* arg2 = traptype */
1631 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1633 move %icc, T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
1649 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g3)
1653 mov T_INSTR_MMU_MISS, %g3
1656 move %icc, T_DATA_MMU_MISS, %g3
1657 movne %icc, T_DATA_PROT, %g3
1703 sub %g5, 1, %g3
1704 wrpr %g3, %tl
1714 sub %g5, 1, %g3
1715 wrpr %g3, %tl
1794 GET_MMU_D_ADDR(%g3, /*scratch*/ %g4)
1795 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
1803 mov T_DATA_MMU_MISS, %g3 /* arg2 = traptype */
2265 or %g0, RUNTIME_PATCH, %g3 ! ktsb_szcode (hot patched)
2267 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
2272 RUNTIME_PATCH_SETX(%g3, %g6)
2277 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)
2278 ! %g3 = 4M tsb entry pointer, as TSB miss handler expects
2298 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3) /* get 2nd utsbreg */
2299 brlz,pt %g3, 9f /* check for 2nd TSB */
2302 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2308 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2309 brlz,pt %g3, 9f /* check for 2nd TSB */
2312 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2316 mov -1, %g3 /* set second tsbe ptr to -1 */
2319 GET_2ND_TSBE_PTR(%g7, %g1, %g3, %g4, %g5, sfmmu_uprot)
2343 brnz,pn %g3, tsb_tl0_noctxt
2360 srlx %g2, MMU_PAGESHIFT4M, %g3 ! use 4m virt-page as TSB index
2366 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2373 sllx %g3, 64-(TSB_START_SIZE + RUNTIME_PATCH), %g3
2374 srlx %g3, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g3
2375 add %g4, %g3, %g3 ! %g3 = 4m tsbe ptr
2376 ldda [%g3]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2383 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2404 brnz,pn %g3, tsb_tl0_noctxt /* invalid context? */
2436 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2460 srlx %g2, MMU_PAGESHIFT4M, %g3
2470 sllx %g3, 64-(TSB_START_SIZE + RUNTIME_PATCH), %g3
2471 srlx %g3, 64-(TSB_START_SIZE + TSB_ENTRY_SHIFT + RUNTIME_PATCH), %g3
2478 ldda [%g7 + %g3]RUNTIME_PATCH, %g4 ! %g4 = tag, %g5 = data
2484 add %g7, %g3, %g3 ! %g3 = kernel second TSB ptr
2487 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2535 mov -1, %g3
2554 mov -1, %g3
2579 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2582 PROBE_2ND_ITSB(%g3, %g7)
2622 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2623 brlz,pt %g3, 2f
2625 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2626 PROBE_2ND_ITSB(%g3, %g7, uitlb_4m_probefail)
2637 mov %g1, %g3 /* save tsb8k reg in %g3 */
2638 GET_1ST_TSBE_PTR(%g3, %g1, %g5, sfmmu_uitlb)
2641 mov %g3, %g7 /* copy tsb8k reg in %g7 */
2642 GET_2ND_TSBE_PTR(%g6, %g7, %g3, %g4, %g5, sfmmu_uitlb)
2645 PROBE_2ND_ITSB(%g3, %g7, isynth)
2682 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2683 brlz,pt %g3, 1f
2685 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2686 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
2740 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3)
2741 brlz,pt %g3, 5f
2743 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2744 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail2)
2768 mov %g1, %g3
2803 ldxa [%g0]ASI_DMMU_TSB_8K, %g3
2818 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2821 mov %g3, %g7
2822 GET_2ND_TSBE_PTR(%g2, %g7, %g3, %g4, %g5, sfmmu_udtlb)
2829 PROBE_2ND_DTSB(%g3, %g7, udtlb_4m_probefail)
2874 stn %g3, [%g6 + TSBMISS_TSBPTR4M] /* save 2ND tsb pointer */
2876 sllx %g2, TAGACC_CTX_LSHIFT, %g3
2877 brz,a,pn %g3, 1f /* skip ahead if kernel */
2879 srlx %g3, TAGACC_CTX_LSHIFT, %g3 /* g3 = ctxnum */
2884 cmp %g3, INVALID_CONTEXT
2894 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
2912 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2941 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2958 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2979 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2997 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3011 brlz,a,pt %g3, tsb_validtte
3032 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3047 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3061 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3076 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3091 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3098 brgez,pn %g3, tsb_pagefault
3132 TTE_SET_REFMOD_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_refmod,
3152 andcc %g3, TTE_EXECPRM_INT, %g0 /* check execute bit is set */
3155 andcc %g3, TTE_EXECPRM_INT, %g0 /* check execute bit is set */
3164 TTE_SET_REF_ML(%g3, %g4, %g6, %g7, %g5, tsb_lset_ref)
3205 and %g3, TTE_SZ_BITS, %g7 ! assumes TTE_SZ_SHFT is 0
3207 srlx %g3, TTE_SZ_SHFT, %g7
3218 srlx %g3, TTE_SZ2_SHFT, %g7
3249 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3255 mov %g3, %g5
3259 mov %g3, %g5
3261 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3265 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3292 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3299 mov %g3, %g5
3303 mov %g3, %g5
3305 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3309 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3335 andcc %g3, TTE_EXECPRM_INT, %g0 /* is execprm bit set */
3339 mov %g3, %g5
3343 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 1) /* make 4M pfn offset */
3347 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3349 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3357 GET_4M_PFN_OFF(%g3, %g6, %g5, %g7, 2) /* make 4M pfn offset */
3359 or %g5, %g3, %g5 /* add 4M bits to TTE */
3363 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3366 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3393 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3398 mov %g3, %g5 ! trapstat wants TTE in %g5
3402 mov %g3, %g5 ! trapstat wants TTE in %g5
3403 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3407 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3428 srlx %g3, %g4, %g3 /* clr size field */
3430 sllx %g3, %g4, %g3 /* g3 = ism vbase */
3433 sub %g1, %g3, %g2 /* g2 = offset in ISM seg */
3445 SAVE_CTX1(%g5, %g3, %g1, tsb_shctxl)
3473 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3479 brlz,a,pt %g3, tsb_validtte
3492 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3497 brlz,a,pt %g3, tsb_validtte
3504 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3510 brlz,a,pt %g3, tsb_validtte
3518 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3524 brlz,a,pt %g3, tsb_validtte
3567 add %sp, STACK_BIAS, %g3
3568 srlx %g3, MMU_PAGESHIFT, %g3
3570 cmp %g3, %g4
3603 GET_MMU_D_ADDR(%g3, %g4)
3604 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3630 GET_MMU_D_ADDR(%g3, %g4)
3631 stx %g3, [%g1 + CPUC_DTRACE_ILLVAL]
3658 GET_MMU_D_ADDR(%g3, %g4)
3659 stx %g3, [%g5 + CPUC_DTRACE_ILLVAL]
3680 ldx [%g2 + MMFSA_I_CTX], %g3
3683 ldx [%g2 + MMFSA_I_CTX], %g3
3684 ldx [%g2 + MMFSA_D_CTX], %g3
3689 ldxa [%g2]ASI_IMMU, %g3
3690 ldxa [%g2]ASI_DMMU, %g3
3691 2: sllx %g3, TAGACC_CTX_LSHIFT, %g3
3693 brz,a,pn %g3, ptl1_panic ! panic if called for kernel
3759 GET_TTE(%o0, %o4, %g1, %g2, %o5, %g4, %g6, %g5, %g3,
3776 TTETOPFN(%g1, %o0, vatopfn_l2, %g2, %g3, %g4)
3900 GET_TTE(%o0, %o4, %g3, %g4, %g1, %o5, %g6, %o1, %g5,
3909 brgez,a,pn %g3, 1f /* check if tte is invalid */
3911 TTETOPFN(%g3, %o0, kvaszc2pfn_l2, %g2, %g4, %g5)
3916 mov %g3, %o0
4029 stx %g3, [%g6 + KPMTSBM_TSBPTR]
4037 and %g4, KPMTSBM_TLTSBM_FLAG, %g3
4039 brz,pn %g3, sfmmu_kpm_exception
4055 ldub [%g6 + KPMTSBM_SZSHIFT], %g3
4057 srax %g4, %g3, %g2 /* which alias range (r) */
4068 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmp2m)
4069 cmp %g3, MSEG_NULLPTR_PA
4078 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4089 ldxa [%g3 + MEMSEG_KPM_NKPMPGS]%asi, %g5
4100 ldxa [%g3 + MEMSEG_KPM_PAGES]%asi, %g5 /* kpm_pages */
4117 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_pagespa */
4126 add %g4, %g5, %g3
4127 add %g3, KPMHLK_LOCK, %g3 /* hlck_pa */
4159 KPMLOCK_ENTER(%g3, %g7, kpmtsbmhdlr1, ASI_MEM)
4195 KPMLOCK_EXIT(%g3, ASI_MEM)
4220 KPMLOCK_EXIT(%g3, ASI_MEM)
4285 ldub [%g6 + KPMTSBM_SZSHIFT], %g3 /* g3 = kpm_size_shift */
4287 srax %g4, %g3, %g7 /* which alias range (r) */
4294 sllx %g7, %g3, %g5 /* g5 = r << kpm_size_shift */
4328 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmsp2m)
4329 cmp %g3, MSEG_NULLPTR_PA
4337 ldxa [%g3 + MEMSEG_KPM_PBASE]%asi, %g7
4345 ldxa [%g3 + MEMSEG_KPM_NKPMPGS]%asi, %g5
4353 ldxa [%g3 + MEMSEG_KPM_SPAGES]%asi, %g5
4372 ldxa [%g3 + MEMSEG_KPM_PAGESPA]%asi, %g1 /* kpm_spagespa */
4383 add %g4, %g5, %g3 /* hlck_pa */
4406 KPMLOCK_ENTER(%g3, %g7, kpmtsbsmlock, ASI_MEM)
4439 KPMLOCK_EXIT(%g3, ASI_MEM)
4464 KPMLOCK_EXIT(%g3, ASI_MEM)
4570 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) ! %g2 = ptagacc, %g3 = ctx type
4577 brnz,pt %g3, 8f ! check for user context
4589 or %g0, RUNTIME_PATCH, %g3 ! ktsb_szcode (hot patched)
4591 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
4596 RUNTIME_PATCH_SETX(%g3, %g6) ! %g3 = contents of ktsb4m_pbase
4600 GET_TSBE_POINTER(MMU_PAGESHIFT4M, %g3, %g7, %g6, %g5)
4601 ! %g3 = 4M tsb entry pointer, as TSB miss handler expects
4615 GET_UTSBREG(SCRATCHPAD_UTSBREG2, %g3) /* get 2nd utsbreg */
4616 brlz,pt %g3, sfmmu_tsb_miss_tt /* done if no 2nd TSB */
4619 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
4636 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3)