Lines Matching full:g2
581 lduw [%o2 + CPU_MMU_IDX], %g2 ! %g2 = mmu index
608 sllx %g2, SFMMU_MMU_CTX_SHIFT, %g2
609 add %o0, %g2, %g2 ! %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
614 * %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
619 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
667 * %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
670 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
709 * %g2 = &sfmmu_ctx_t[mmuid] - SFMMU_CTXS;
756 stx %o4, [%g2 + SFMMU_CTXS]
803 ldx [%o1], %g2 /* modified */
804 cmp %g2, %g3 /* is modified = current? */
807 casx [%o2], %g1, %g2
808 cmp %g1, %g2
820 ldx [%o1], %g2 /* modified */
823 cmp %g3, %g2 /* is modified = current? */
827 casx [%o2], %g1, %g2
829 cmp %g1, %g2
833 stx %g2, [%o0] /* report "current" value */
1359 TSB_UPDATE(%o0, %o2, %o1, %g1, %g2, locked_tsb_l8)
1408 GET_KPM_TSBE_POINTER(%o2, %g2, %g1, %o3, %o4)
1409 /* %g2 = tsbep, %g1 clobbered */
1413 TSB_UPDATE(%g2, %o1, %g1, %o3, %o4, locked_tsb_l9)
1440 GET_KPM_TSBE_POINTER(%o1, %g2, %g1, %o3, %o4)
1441 /* %g2 = tsbep, %g1 clobbered */
1445 TSB_INVALIDATE(%g2, %g1, %o3, %o4, %o1, kpm_tsbinval)
1454 TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
1579 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g6, %g4)
1587 mov %g5, %g2
1606 * g2 = tag access reg
1620 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g6)
1628 mov %g5, %g2
1636 * g2 = tag access reg
1649 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g3)
1654 mov %g5, %g2
1661 /* g1 = TL0 handler, g2 = tagacc, g3 = trap type */
1705 rdpr %tt, %g2
1716 rdpr %tt, %g2
1719 and %g2, WTRAP_TTMASK, %g4
1785 CPU_INDEX(%g1, %g2)
1786 set cpu_core, %g2
1788 add %g1, %g2, %g1
1789 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
1790 andcc %g2, CPU_DTRACE_NOFAULT, %g0
1792 or %g2, CPU_DTRACE_BADADDR, %g2
1793 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
1798 TSTAT_CHECK_TL1(1f, %g1, %g2)
1802 GET_MMU_D_TAGACC(%g2 /* tagacc */, %g4 /*scratch*/)
1805 * g2=tagacc g3.l=type g3.h=0
2253 * g2 = tag access register (ro)
2260 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2270 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2289 * g2 = tag access register (ro)
2295 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2296 /* %g1 = first TSB entry ptr now, %g2 preserved */
2302 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2303 /* %g3 = second TSB entry ptr now, %g2 preserved */
2312 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2313 /* %g3 = second TSB entry ptr now, %g2 preserved */
2318 mov %g2, %g7
2337 * %g2 = tag access register (used)
2354 iktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2360 srlx %g2, MMU_PAGESHIFT4M, %g3 ! use 4m virt-page as TSB index
2366 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2383 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2399 * %g2 = tag access register (used)
2409 KPM_TLBMISS_STAT_INCR(%g2, %g4, %g5, %g6, kpmtlbm_stat_out)
2422 dktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2431 srlx %g2, TAG_VALO_SHIFT, %g6 ! make tag to compare
2436 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2449 brlz,pn %g2, sfmmu_kpm_dtsb_miss_small
2458 * %g2 = tag access register (we still need it)
2460 srlx %g2, MMU_PAGESHIFT4M, %g3
2479 srlx %g2, TAG_VALO_SHIFT, %g6 ! make tag to compare
2487 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2507 * g2 = tag access register
2511 cmp %g2, %g0
2525 * g2 = tag access register
2544 * g2 = tag access register
2568 * g2 = tag access register
2575 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2579 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2581 srlx %g2, TAG_VALO_SHIFT, %g7
2607 * g2 = tag access register
2619 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2625 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2631 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2640 mov %g2, %g6 /* GET_2ND_TSBE_PTR clobbers tagacc */
2644 srlx %g2, TAG_VALO_SHIFT, %g7
2664 * g2 = tag access register
2685 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2695 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2705 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2715 * g2 = tag access register
2733 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2743 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2755 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2766 srax %g2, PREDISM_BASESHIFT, %g6 /* g6 > 0 : ISM predicted */
2773 * g2 = tag access register
2779 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2785 * g2 = tag access reg
2798 * g2 = tag access reg
2811 * g2 = tag access reg
2818 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2819 /* %g2 is okay, no need to reload, %g3 = second tsbe ptr */
2822 GET_2ND_TSBE_PTR(%g2, %g7, %g3, %g4, %g5, sfmmu_udtlb)
2823 /* %g2 clobbered, %g3 =second tsbe ptr */
2824 mov MMU_TAG_ACCESS, %g2
2825 ldxa [%g2]ASI_DMMU, %g2
2828 srlx %g2, TAG_VALO_SHIFT, %g7
2844 * g2 = tag access register
2876 sllx %g2, TAGACC_CTX_LSHIFT, %g3
2894 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
2899 * %g2 = (pseudo) tag access
2912 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2918 sllx %g2, TAGACC_CTX_LSHIFT, %g5
2941 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2947 sllx %g2, TAGACC_CTX_LSHIFT, %g5
2958 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2964 sllx %g2, TAGACC_CTX_LSHIFT, %g5
2979 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
2997 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3005 * g2 = tagacc
3022 * g2 = tagacc
3025 sllx %g2, TAGACC_CTX_LSHIFT, %g5
3032 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3047 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3061 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3076 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3091 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3114 SAVE_CTX1(%g7, %g2, %g1, tsb_shmel)
3135 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
3174 MMU_FAULT_STATUS_AREA(%g2)
3181 add %g2, MMFSA_D_, %g2
3183 ldx [%g2 + MMFSA_CTX_], %g7
3185 ldx [%g2 + MMFSA_ADDR_], %g2
3186 mov %g2, %g5 ! load the fault addr for later use
3187 srlx %g2, TTARGET_VA_SHIFT, %g2
3188 or %g2, %g7, %g2
3193 ldxa [%g0]ASI_IMMU, %g2
3194 ldxa [%g0]ASI_DMMU, %g2
3202 srlx %g2, TTARGET_CTX_SHIFT, %g7
3249 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3261 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3265 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3292 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3305 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3309 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3325 * g2 = tagtarget
3347 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3349 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3363 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3366 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3393 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3403 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3407 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3416 * g2 = vaddr + ctx(or ctxtype (sun4v)) aka (pseudo-)tag access
3431 and %g2, %g1, %g4 /* g4 = ctx number */
3432 andn %g2, %g1, %g1 /* g1 = tlb miss vaddr */
3433 sub %g1, %g3, %g2 /* g2 = offset in ISM seg */
3434 or %g2, %g4, %g2 /* g2 = (pseudo-)tagacc */
3453 * g2 = tagacc w/ISM vaddr (offset in ISM seg)
3473 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3492 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3504 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3518 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3557 ldxa [%g4]ASI_DMMU, %g2
3559 move %icc, %g5, %g2
3561 move %icc, %g5, %g2
3562 sllx %g2, TAGACC_CTX_LSHIFT, %g4
3569 srlx %g2, MMU_PAGESHIFT, %g4
3577 TSTAT_CHECK_TL1(2f, %g1, %g2)
3578 rdpr %tt, %g2
3579 cmp %g2, FAST_PROT_TT
3594 CPU_INDEX(%g1, %g2)
3595 set cpu_core, %g2
3597 add %g1, %g2, %g1
3598 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3599 andcc %g2, CPU_DTRACE_NOFAULT, %g0
3601 or %g2, CPU_DTRACE_BADADDR, %g2
3602 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3611 TSTAT_CHECK_TL1(4f, %g1, %g2)
3621 CPU_INDEX(%g1, %g2)
3622 set cpu_core, %g2
3624 add %g1, %g2, %g1
3625 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3626 andcc %g2, CPU_DTRACE_NOFAULT, %g0
3628 or %g2, CPU_DTRACE_BADADDR, %g2
3629 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3638 rdpr %tstate, %g2
3639 btst TSTATE_PRIV, %g2
3670 TSTAT_CHECK_TL1(2f, %g1, %g2);
3678 MMU_FAULT_STATUS_AREA(%g2)
3680 ldx [%g2 + MMFSA_I_CTX], %g3
3683 ldx [%g2 + MMFSA_I_CTX], %g3
3684 ldx [%g2 + MMFSA_D_CTX], %g3
3687 mov MMU_TAG_ACCESS, %g2
3689 ldxa [%g2]ASI_IMMU, %g3
3690 ldxa [%g2]ASI_DMMU, %g3
3699 TSTAT_CHECK_TL1(sfmmu_mmu_trap, %g1, %g2)
3759 GET_TTE(%o0, %o4, %g1, %g2, %o5, %g4, %g6, %g5, %g3,
3768 * g2 = tte pa
3776 TTETOPFN(%g1, %o0, vatopfn_l2, %g2, %g3, %g4)
3823 * g2 = tte pa
3911 TTETOPFN(%g3, %o0, kvaszc2pfn_l2, %g2, %g4, %g5)
4004 * g2 = tag access register
4024 cmp %g2, %g7
4027 cmp %g2, %g5
4048 * g2 = tag access register
4056 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4057 srax %g4, %g3, %g2 /* which alias range (r) */
4058 brnz,pn %g2, sfmmu_kpm_exception /* if (r != 0) goto C handler */
4059 srlx %g4, MMU_PAGESHIFT, %g2 /* %g2 = pfn */
4065 * g2=pfn
4068 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmp2m)
4075 * g2=pfn g3=mseg_pa
4079 srlx %g2, %g5, %g4
4086 * g2=pfn g3=mseg_pa g4=inx
4105 * g2=pfn g3=mseg_pa g4=offset g5=kp g7=kpmp_table_sz
4115 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4122 * g1=kp_refcntc_pa g2=pfn g5=hashinx
4131 * g1=kp_pa g2=pfn g3=hlck_pa
4148 sllx %g2, MMU_PAGESHIFT, %g4
4151 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4155 * g1=kp_pa g2=ttarget g3=hlck_pa g4=kpmtsbp4m g5=tte g6=kpmtsbm_area
4190 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4192 DTLB_STUFF(%g5, %g1, %g2, %g4, %g6)
4228 * g2 = tag access register
4250 cmp %g2, %g7
4253 cmp %g2, %g5
4274 * g2 = tag access register
4286 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4292 srlx %g2, MMU_PAGESHIFT, %g1 /* vaddr >> MMU_PAGESHIFT */
4310 * g2 = tag access register
4318 srlx %g4, MMU_PAGESHIFT, %g2 /* g2 = pfn */
4324 * g2=pfn g6=per-CPU kpm tsbmiss area
4328 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmsp2m)
4335 * g2=pfn g3=mseg_pa g6=per-CPU kpm tsbmiss area
4338 sub %g2, %g7, %g4
4343 * g2=pfn g3=mseg_pa g4=inx g6=per-CPU tsbmiss area
4358 * g2=pfn g3=mseg_pa g4=inx g5=ksp
4369 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4378 * g1=ksp_pa g2=pfn g5=hashinx
4387 * g1=ksp_pa g2=pfn g3=hlck_pa
4394 sllx %g2, MMU_PAGESHIFT, %g4
4397 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4401 * g1=ksp_pa g2=ttarget g3=hlck_pa g4=ktsbp g5=tte (non-cacheable)
4434 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4436 DTLB_STUFF(%g5, %g2, %g4, %g5, %g6)
4570 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) ! %g2 = ptagacc, %g3 = ctx type
4574 * %g2 = tagacc register (needed for sfmmu_tsb_miss_tt)
4585 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4594 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4612 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
4613 /* %g1 = first TSB entry ptr now, %g2 preserved */
4619 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
4620 /* %g3 = second TSB entry ptr now, %g2 preserved */
4636 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3)