Lines Matching +full:ls +full:- +full:bits

88  * Data Cache (DC) bank error-detection enabling bits and CTL register
105  * Instruction Cache (IC) bank error-detection enabling bits and CTL register
126  * Bus Unit (BU) bank error-detection enabling bits and CTL register
166  * Load/Store (LS) bank error-detection enabling bits and CTL register
170  * error the LS unit can detect at present, so we won't be enabling any
171  * LS detectors.
180  * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register.
193  * and a NB-specific configuration register (NB CFG).  The AMD_NB_EN_* macros
194  * are the detector enabling bits for the NB MCA CTL register.  The
195  * AMD_NB_CFG_* bits are for the NB CFG register.
201  * via and MSR write of 64 bits so define all as ULL.
226 #define	AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \
254  * selectively add some bits and remove others.  Note that
256  * story here - additional config is performed regarding the watchdog (see
299  * The AMD extended error code is just one nibble of the upper 16 bits
332 #define	AMD_NB_STAT_CKSYND_SHIFT	(24 - 8) /* shift [31:24] to [15:8] */