Lines Matching +full:num +full:- +full:cs
42 * AMD cpu module and the mc-amd driver.
46 * The mc-amd driver exports an nvlist to userland, where the primary
52 * In the initial mc-amd implementation this nvlist was not versioned;
54 * of a "mcamd-nvlist-version member.
60 * -------------------- --------------- ---------------------------------------
61 * mcamd-nvlist-version uint8 Exported nvlist version number
62 * num uint64 Chip id of this memory controller
66 * ecc-type string "ChipKill 128/16" or "Normal 64/8"
67 * base-addr uint64 Node base address
68 * lim-addr uint64 Node limit address
69 * node-ilen uint64 0|1|3|7 for 0/2/4/8 way node interleave
70 * node-ilsel uint64 Node interleave position of this node
71 * cs-intlv-factor uint64 chip-select interleave: 1/2/4/8
72 * dram-hole-size uint64 size in bytes from dram hole addr reg
73 * access-width uint64 MC mode, 64 or 128 bit
74 * bank-mapping uint64 Raw DRAM Bank Address Mapping Register
76 * mismatched-dimm-support uint64 1 if active; else 0
77 * [spare-csnum] uint64 Chip-select pair number of any spare
78 * [bad-csnum] uint64 Chip-select pair number of swapped cs
85 * -------------------- --------------- ---------------------------------------
86 * num uint64 Chip-select base/mask pair number
87 * base-addr uint64 Chip-select base address (rel to node)
88 * mask uint64 Chip-select mask
89 * size uint64 Chip-select size in bytes
90 * dimm1-num uint64 First dimm (lodimm if a pair)
91 * dimm1-csname string Socket cs# line name for 1st dimm rank
92 * [dimm2-num] uint64 Second dimm if applicable (updimm)
93 * [dimm2-csname] string Socket cs# line name for 2nd dimm rank
98 * -------------------- --------------- ---------------------------------------
99 * num uint64 DIMM instance number
101 * csnums uint64 array CS base/mask pair(s) on this DIMM
102 * csnames string array Socket cs# line name(s) on this DIMM
106 #define MC_NVLIST_VERSTR "mcamd-nvlist-version"
121 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */
124 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */
137 #define MC_AMD_DEV_OFFSET 0x18 /* node ID + offset == PCI dev num */
148 * desired register. All registers are 32-bits wide.
152 * where DDR2 support has been introduced along with some hardware-controlled
154 * required by the mc-amd driver is similar across revisions.
157 * details by reading all memory-controller PCI config registers that we
183 * Function 2 (dram controller) offsets for chip-select base, chip-select mask,
186 #define MC_DC_REG_CS_INCR 4 /* incr for CS base and mask */
187 #define MC_DC_REG_CSBASE_0 0x40 /* 0x40 - 0x5c */
188 #define MC_DC_REG_CSMASK_0 0x60 /* 0x60 - 0x7c */
202 #define MC_CTL_REG_SPARECTL 0xb0 /* On-line spare control register */
218 ((j) == 0 ? MC_MSR_NB_MISC0 : MC_MSR_NB_MISC1 + (j) - 1)
221 * PCI registers will be represented as unions, with one fixed-width unsigned
232 * 'cmn' - applies to all revisions
233 * 'f_preF' - applies to revisions E and earlier
234 * 'f_revFG' - applies to revisions F and G
279 #define _MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
281 #define MCREG_VAL32(up) ((up)->_val32)
304 * We will only define the register bitfields for little-endian order
309 * Function 0 - HT Configuration: Routing Table Node Register
324 * Function 0 - HT Configuration: Node ID Register
346 * Function 0 - HT Configuration: Unit ID Register
361 * Function 1 - DRAM Address Map: DRAM Base i Registers
368 uint32_t RE:1; /* 0:0 - Read Enable */
369 uint32_t WE:1; /* 1:1 - Write Enable */
371 uint32_t IntlvEn:3; /* 10:8 - Interleave Enable */
373 uint32_t DRAMBasei:16; /* 31:16 - Base Addr 39:24 */
380 * Function 1 - DRAM Address Map: DRAM Limit i Registers
387 uint32_t DstNode:3; /* 2:0 - Destination Node */
389 uint32_t IntlvSel:3; /* 10:8 - Interleave Select */
391 uint32_t DRAMLimiti:16; /* 31:16 - Limit Addr 39:24 */
397 (MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0))
400 * Function 1 - DRAM Address Map: DRAM Hole Address Register
417 * Function 2 - DRAM Controller: DRAM CS Base Address Registers
426 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */
428 uint32_t BaseAddrLo:7; /* 15:9 - Base Addr 19:13 */
430 uint32_t BaseAddrHi:11; /* 31:21 - Base Addr 35:25 */
436 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */
437 uint32_t Spare:1; /* 1:1 - Spare Rank */
438 uint32_t TestFail:1; /* 2:2 - Memory Test Failed */
440 uint32_t BaseAddrLo:9; /* 13:5 - Base Addr 21:13 */
442 uint32_t BaseAddrHi:10; /* 28:19 - Base Addr 36:27 */
454 * Function 2 - DRAM Controller: DRAM CS Mask Registers
464 uint32_t AddrMaskLo:7; /* 15:9 - Addr Mask 19:13 */
466 uint32_t AddrMaskHi:9; /* 29:21 - Addr Mask 33:25 */
474 uint32_t AddrMaskLo:9; /* 13:5 - Addr Mask 21:13 */
476 uint32_t AddrMaskHi:10; /* 28:19 - Addr Mask 36:27 */
496 * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers
505 uint32_t cs10:4; /* 3:0 - CS1/0 */
506 uint32_t cs32:4; /* 7:4 - CS3/2 */
507 uint32_t cs54:4; /* 11:8 - CS5/4 */
508 uint32_t cs76:4; /* 15:12 - CS7/6 */
517 uint32_t cs10:4; /* 3:0 - CS1/0 */
518 uint32_t cs32:4; /* 7:4 - CS3/2 */
519 uint32_t cs54:4; /* 11:8 - CS5/4 */
520 uint32_t cs76:4; /* 15:12 - CS7/6 */
535 #define MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >> \
539 * Function 2 - DRAM Controller: DRAM Configuration Low and High
600 * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data
672 * Function 3 - Miscellaneous Control: Scrub Control Register
705 * Function 3 - Miscellaneous Control: On-Line Spare Control Register
775 * Function 3 - Miscellaneous Control: On-Line Spare Control Register
823 * Since the NB is on-chip some registers are also accessible as MSRs.
824 * We will represent such registers as bitfields as in the 32-bit PCI
825 * registers above, with the restriction that we must compile for 32-bit
826 * kernels and so 64-bit bitfields cannot be used.
829 #define _MCMSR_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
831 #define MCMSR_VAL(up) ((up)->_val64)
840 * a 12-bit ECC error count of all ECC errors observed on this memory-
841 * controller (regardless of channel or chip-select) and the ability to