Lines Matching +full:8 +full:- +full:channel
38 #define D37A_MAX_CHAN 8
47 * The PC/AT has two Intel 8237A-5 DMA controllers that provide 8 channels
49 #define DMA_0WCNT 0x01 /* Channel word count */
50 #define DMA_1WCNT 0x03 /* Channel word count */
51 #define DMA_2WCNT 0x05 /* Channel word count */
52 #define DMA_3WCNT 0x07 /* Channel word count */
53 #define DMA_4WCNT 0xC2 /* (RESERVED) Channel word count */
54 #define DMA_5WCNT 0xC6 /* Channel word count */
55 #define DMA_6WCNT 0xCA /* Channel word count */
56 #define DMA_7WCNT 0xCE /* Channel word count */
58 #define DMA_0ADR 0x00 /* Channel address register */
59 #define DMA_1ADR 0x02 /* Channel address register */
60 #define DMA_2ADR 0x04 /* Channel address register */
61 #define DMA_3ADR 0x06 /* Channel address register */
62 #define DMA_4ADR 0xC0 /* (RESERVED) Channel address register */
63 #define DMA_5ADR 0xC4 /* Channel address register */
64 #define DMA_6ADR 0xC8 /* Channel address register */
65 #define DMA_7ADR 0xCC /* Channel address register */
68 * The Intel DMA controllers are augmented with 8-bit page registers
69 * for each channel, allowing access to a 16MB address space.
71 #define DMA_0PAGE 0x87 /* Channel 0 address extension reg */
72 #define DMA_1PAGE 0x83 /* Channel 1 address extension reg */
73 #define DMA_2PAGE 0x81 /* Channel 2 address extension reg */
74 #define DMA_3PAGE 0x82 /* Channel 3 address extension reg */
76 #define DMA_5PAGE 0x8B /* Channel 5 address extension reg */
77 #define DMA_6PAGE 0x89 /* Channel 6 address extension reg */
78 #define DMA_7PAGE 0x8A /* Channel 7 address extension reg */
81 * The EISA has an 8-bit high-page register for each channel
82 * for access to a 32-bit address space.
84 #define DMA_0HPG 0x487 /* port address for dma channel 0 */
86 #define DMA_1HPG 0x483 /* port address for dma channel 1 */
88 #define DMA_2HPG 0x481 /* port address for dma channel 2 */
90 #define DMA_3HPG 0x482 /* port address for dma channel 3 */
92 #define DMA_4HPG 0 /* dummy address for dma channel 4 */
94 #define DMA_5HPG 0x48B /* port address for dma channel 5 */
96 #define DMA_6HPG 0x489 /* port address for dma channel 6 */
98 #define DMA_7HPG 0x48A /* port address for dma channel 7 */
102 * The EISA has an 8-bit high-count register for each channel
122 #define DMAC1_CLFF 0x0C /* Clear byte pointer first/last flip-flop */
137 #define DMAC2_CLFF 0xD8 /* Clear byte pointer first/last flip-flop */
145 * Write-only Command register definitions.
147 #define DMACMD_MEM_TO_MEM 0x01 /* memory-to-memory copy (1=enable) */
148 #define DMACMD_CHAN_HOLD 0x02 /* Channel 0 address hold (1=enable) */
165 * Write-only Mode register. There is actually a 6-bit Mode register
166 * associated with each channel. These are written one at a time, with
167 * the channel number indicated by the low-order 2 bits.
170 #define DMAMODE_CHAN 0x03 /* Mask for the "channel select" bits. */
171 /* These indicate channel 0-3 */
175 /* Note: Above settings for bits 2-3 are */
176 /* "don't care" if bits 6-7 indicate */
183 /* can be resumed) or either terminal-count */
190 #define DMAMODE_CASC 0xC0 /* Select Cascade mode. On the PC-AT, this */
191 /* should be set for DMA 2 channel 0 ONLY */
204 /* 8 bit channels */
205 #define DMAE_CH0 0 /* Channel 0 */
206 #define DMAE_CH1 1 /* Channel 1 */
207 #define DMAE_CH2 2 /* Channel 2 */
208 #define DMAE_CH3 3 /* Channel 3 */
209 #define DMAE_CH4 4 /* Channel 4 */
211 #define DMAE_CH5 5 /* Channel 5 */
212 #define DMAE_CH6 6 /* Channel 6 */
213 #define DMAE_CH7 7 /* Channel 7 */
223 #define DMA_NBLOCK 1 /* non-blocking task time allocation */
225 #define EISA_DMA_8 0 /* 8-bit data path */
226 #define EISA_DMA_16 1<<2 /* 16-bit data path, word count */
227 #define EISA_DMA_32 2<<2 /* 32-bit data path */
228 #define EISA_DMA_16B 3<<2 /* 16-bit data path, byte count */
231 #define EISA_CMOK 8 /* chaining mode completed (OK) */
235 * Channel Address Array - makes life much easier
241 uchar_t ff_reg; /* first-last flipflop */