Lines Matching refs:srd_reg
99 ASSERT0(def.srd_reg & APERTURE_MASK); in amdzen_umc_smn_reg()
109 const uint32_t reg = def.srd_reg + reginst32 * stride; in amdzen_umc_smn_reg()
123 .srd_reg = 0x00, \
129 .srd_reg = 0x10, \
146 .srd_reg = 0xb00, \
152 .srd_reg = 0xb10, \
170 .srd_reg = 0x20, \
176 .srd_reg = 0x28, \
182 .srd_reg = 0x20, \
188 .srd_reg = 0x30, \
204 .srd_reg = 0xb20, \
210 .srd_reg = 0xb30, \
231 .srd_reg = 0x30, \
237 .srd_reg = 0x40, \
264 .srd_reg = 0x40, \
270 .srd_reg = 0x50, \
297 .srd_reg = 0x50, \
304 .srd_reg = 0x54, \
311 .srd_reg = 0x60, \
318 .srd_reg = 0x64, \
348 .srd_reg = 0x70, \
354 .srd_reg = 0x78, \
370 .srd_reg = 0x80, \
391 .srd_reg = 0x80, \
397 .srd_reg = 0x90, \
427 .srd_reg = 0xc8, \
433 .srd_reg = 0x98, \
452 .srd_reg = 0xdc, \
458 .srd_reg = 0xb0, \
475 .srd_reg = 0xbb0, \
492 .srd_reg = 0xc0 \
497 .srd_reg = 0xc4 \
515 .srd_reg = 0xe8, \
521 .srd_reg = 0xc8, \
536 .srd_reg = 0xbc8, \
552 .srd_reg = 0x100 \
576 .srd_reg = 0x144 \
596 .srd_reg = 0x14c \
646 .srd_reg = 0x200, \
744 .srd_reg = 0xdf0 \
749 .srd_reg = 0xdf4 \