132 #define	UMC_BASE(u, i)		amdzen_umc_smn_reg(u, D_UMC_BASE, i)  argument
133 #define	UMC_BASE_SEC(u, i)	amdzen_umc_smn_reg(u, D_UMC_BASE_SEC, i)  argument
155 #define	UMC_BASE_EXT_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_DDR5, i)  argument
156 #define	UMC_BASE_EXT_SEC_DDR5(u, i)	\  argument
157     amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_SEC_DDR5, i)
191 #define	UMC_MASK_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_MASK_DDR4, i)  argument
192 #define	UMC_MASK_SEC_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR4, i)  argument
193 #define	UMC_MASK_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_MASK_DDR5, i)  argument
194 #define	UMC_MASK_SEC_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR5, i)  argument
213 #define	UMC_MASK_EXT_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_DDR5, i)  argument
214 #define	UMC_MASK_EXT_SEC_DDR5(u, i)	\  argument
215     amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_SEC_DDR5, i)
240 #define	UMC_ADDRCFG_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR4, i)  argument
241 #define	UMC_ADDRCFG_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR5, i)  argument
273 #define	UMC_ADDRSEL_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR4, i)  argument
274 #define	UMC_ADDRSEL_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR5, i)  argument
322 #define	UMC_COLSEL_LO_DDR4(u, i)	\  argument
323     amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR4, i)
324 #define	UMC_COLSEL_HI_DDR4(u, i)	\  argument
325     amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR4, i)
326 #define	UMC_COLSEL_LO_DDR5(u, i)	\  argument
327     amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR5, i)
328 #define	UMC_COLSEL_HI_DDR5(u, i)	\  argument
329     amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR5, i)
357 #define	UMC_RMSEL_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR4, i)  argument
358 #define	UMC_RMSEL_SEC_DDR4(u, i)	\  argument
359     amdzen_umc_smn_reg(u, D_UMC_RMSEL_SEC_DDR4, i)
373 #define	UMC_RMSEL_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR5, i)  argument
400 #define	UMC_DIMMCFG_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR4, i)  argument
401 #define	UMC_DIMMCFG_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR5, i)  argument
436 #define	UMC_BANK_HASH_DDR4(u, i)	\  argument
437     amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR4, i)
438 #define	UMC_BANK_HASH_DDR5(u, i)	\  argument
439     amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR5, i)
461 #define	UMC_RANK_HASH_DDR4(u, i)	\  argument
462     amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR4, i)
463 #define	UMC_RANK_HASH_DDR5(u, i)	\  argument
464     amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR5, i)
478 #define	UMC_RANK_HASH_EXT_DDR5(u, i)	\  argument
479     amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_EXT_DDR5, i)
499 #define	UMC_PC_HASH_DDR4(u)	UMC_RANK_HASH_DDR4(u, 1)  argument
500 #define	UMC_PC_HASH2_DDR4(u)	UMC_RANK_HASH_DDR4(u, 2)  argument
501 #define	UMC_PC_HASH_DDR5(u)	amdzen_umc_smn_reg(u, D_UMC_PC_HASH_DDR5, 0)  argument
502 #define	UMC_PC_HASH2_DDR5(u)	amdzen_umc_smn_reg(u, D_UMC_PC_HASH2_DDR5, 0)  argument
524 #define	UMC_CS_HASH_DDR4(u, i)	amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR4, i)  argument
525 #define	UMC_CS_HASH_DDR5(u, i)	amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR5, i)  argument
539 #define	UMC_CS_HASH_EXT_DDR5(u, i)	\  argument
540     amdzen_umc_smn_reg(u, D_UMC_CS_HASH_EXT_DDR5, i)
554 #define	UMC_UMCCFG(u)	amdzen_umc_smn_reg(u, D_UMC_UMCCFG, 0)  argument
578 #define	UMC_DATACTL(u)		amdzen_umc_smn_reg(u, D_UMC_DATACTL, 0)  argument
598 #define	UMC_ECCCTL(u)	amdzen_umc_smn_reg(u, D_UMC_ECCCTL, 0)  argument
651 #define	UMC_DRAMCFG(u, i)	amdzen_umc_smn_reg(u, D_UMC_DRAMCFG, i)  argument
751 #define	UMC_UMCCAP(u)		amdzen_umc_smn_reg(u, D_UMC_UMCCAP, 0)  argument
756 #define	UMC_UMCCAP_HI(u)	amdzen_umc_smn_reg(u, D_UMC_UMCCAP_HI, 0)  argument