Lines Matching refs:drd_reg
117 uint16_t drd_reg; member
133 .drd_func = 0, .drd_reg = 0x40 }
144 .drd_func = 0, .drd_reg = 0x44 }
231 DF_REV_4, .drd_func = 0, .drd_reg = 0x48 }
243 DF_REV_4, .drd_func = 0, .drd_reg = 0x4c }
253 .drd_func = 0, .drd_reg = 0x50 }
268 .drd_func = 0, .drd_reg = 0x90 }
284 .drd_func = 0, .drd_reg = 0x60 }
287 .drd_func = 0, .drd_reg = 0x68 }
290 .drd_func = 0, .drd_reg = 0x64 }
293 .drd_func = 0, .drd_reg = 0x6c }
304 .drd_func = 7, .drd_reg = 0x180 }
307 .drd_func = 7, .drd_reg = 0x184 }
310 .drd_func = 7, .drd_reg = 0x188 }
313 .drd_func = 7, .drd_reg = 0x18c }
316 .drd_func = 7, .drd_reg = 0x190 }
319 .drd_func = 7, .drd_reg = 0x194 }
322 .drd_func = 7, .drd_reg = 0x198 }
325 .drd_func = 7, .drd_reg = 0x19c }
338 .drd_func = 7, .drd_reg = 0x180 }
341 .drd_func = 7, .drd_reg = 0x184 }
344 .drd_func = 7, .drd_reg = 0x188 }
347 .drd_func = 7, .drd_reg = 0x198 }
350 .drd_func = 7, .drd_reg = 0x19c }
353 .drd_func = 7, .drd_reg = 0x1a0 }
356 .drd_func = 7, .drd_reg = 0x1b0 }
359 .drd_func = 7, .drd_reg = 0x1b4 }
362 .drd_func = 7, .drd_reg = 0x1b8 }
365 .drd_func = 7, .drd_reg = 0x1c8 }
368 .drd_func = 7, .drd_reg = 0x1cc }
371 .drd_func = 7, .drd_reg = 0x1d0 }
381 .drd_reg = 0x84 }
385 .drd_reg = 0xc04 }
396 .drd_reg = 0xa0 + ((x) * 4) }
414 .drd_reg = 0xc80 + ((x) * 8) }
418 .drd_reg = 0xc84 + ((x) * 8) }
436 .drd_reg = 0xc0 + ((x) * 8) }
440 .drd_reg = 0xd00 + ((x) * 8) }
465 .drd_reg = 0xc4 + ((x) * 8) }
469 .drd_reg = 0xd04 + ((x) * 8) }
496 .drd_reg = 0x104 }
500 .drd_reg = 0x104 }
520 .drd_reg = 0x110 + ((r) * 8) }
561 .drd_reg = 0x114 + ((r) * 8) }
588 .drd_reg = 0xe00 + ((x) * 0x10) }
592 .drd_reg = 0x200 + ((x) * 0x10) }
598 .drd_reg = 0xe04 + ((x) * 0x10) }
602 .drd_reg = 0x204 + ((x) * 0x10) }
610 .drd_reg = 0xe08 + ((x) * 0x10) }
614 .drd_reg = 0x208 + ((x) * 0x10) }
637 .drd_reg = 0xe0c + ((x) * 0x10) }
641 .drd_reg = 0x20c + ((x) * 0x10) }
708 .drd_reg = 0x1b4 }
712 .drd_reg = 0x140 + ((r) * 4) }
726 .drd_reg = 0x80 }
730 .drd_reg = 0xc08 }
747 .drd_reg = 0xc10 }
751 .drd_reg = 0xc14 }
755 .drd_reg = 0xc18 }
759 .drd_reg = 0xc1c }
777 .drd_reg = 0x200 + ((x) * 0x10) }
781 .drd_reg = 0x204 + ((x) * 0x10) }
785 .drd_reg = 0xd80 + ((x) * 0x10) }
789 .drd_reg = 0xd84 + ((x) * 0x10) }
797 .drd_reg = 0x208 + ((x) * 0x10) }
801 .drd_reg = 0xd88 + ((x) * 0x10) }
835 .drd_reg = 0xd8c + ((x) * 0x10) }
850 .drd_reg = 0x3F8 }
870 .drd_reg = 0x200 }
886 .drd_reg = 0x200 }
897 .drd_reg = 0x140 }
907 .drd_reg = 0x180 }
921 .drd_reg = 0x204 }
929 .drd_reg = 0x184 }
948 .drd_reg = 0x208 }
963 .drd_reg = 0x208 }
969 .drd_reg = 0x20c }
982 .drd_reg = 0x150 }
986 .drd_reg = 0x1b0 }
992 .drd_reg = 0x154 }
996 .drd_reg = 0x1b4 }
1002 .drd_reg = 0x158 }
1006 .drd_reg = 0x1b8 }
1022 .drd_reg = 0x22c }
1026 .drd_reg = 0x24c }
1052 .drd_reg = 0x104 }
1067 .drd_reg = 0x300 }
1071 .drd_reg = 0x304 }
1075 .drd_reg = 0x140 }
1079 .drd_reg = 0x144 }
1083 .drd_reg = 0x148 }
1087 .drd_reg = 0x14c }
1091 .drd_reg = 0x150 }
1095 .drd_reg = 0x154 }
1106 .drd_reg = 0x90 }
1120 .drd_reg = 0x510 }
1134 .drd_reg = 0x5c }
1139 .drd_reg = 0x8c }
1158 .drd_reg = 0x98}
1162 .drd_reg = 0x9c}
1166 .drd_reg = 0xb8}
1170 .drd_reg = 0xbc}
1194 return ((def.drd_gens & rev) == rev && (def.drd_reg & ~mask) == 0); in df_reg_valid()
1206 .drd_reg = 0x60 }
1213 .drd_reg = 0x190 }
1222 .drd_reg = 0x64 }
1229 .drd_reg = 0x194 }