637 	p4_pcbe_config_t	*cfg = NULL;  in build_cfgs()  local
643 		cfg = (p4_pcbe_config_t *)kcpc_next_config(token, cfg, &daddr);  in build_cfgs()
645 		if (cfg != NULL) {  in build_cfgs()
646 			ASSERT(cfg->p4_picno < 18);  in build_cfgs()
647 			cfgs[cfg->p4_picno] = cfg;  in build_cfgs()
650 				data[cfg->p4_picno] = daddr;  in build_cfgs()
653 	} while (cfg != NULL);  in build_cfgs()
671 	p4_pcbe_config_t	*cfg;  in p4_pcbe_configure()  local
693 		cfg = *data;  in p4_pcbe_configure()
694 		cfg->p4_rawpic = preset & MASK40;  in p4_pcbe_configure()
826 	cfg = (p4_pcbe_config_t *)kmem_alloc(sizeof (p4_pcbe_config_t),  in p4_pcbe_configure()
829 	cfg->p4_flags = 0;  in p4_pcbe_configure()
830 	cfg->p4_picno = picnum;  in p4_pcbe_configure()
831 	cfg->p4_escr_ndx = escr_ndx;  in p4_pcbe_configure()
832 	cfg->p4_escr = (ev->pe_ev << ESCR_EVSEL_SHIFT) |  in p4_pcbe_configure()
836 		cfg->p4_escr |= tag << ESCR_TAG_VALUE_SHIFT;  in p4_pcbe_configure()
837 		cfg->p4_escr |= ESCR_TAG_ENABLE;  in p4_pcbe_configure()
849 			cfg->p4_flags |= P4_THIS_USR;  in p4_pcbe_configure()
851 			cfg->p4_flags |= P4_THIS_SYS;  in p4_pcbe_configure()
853 			cfg->p4_flags |= P4_SIBLING_USR;  in p4_pcbe_configure()
855 			cfg->p4_flags |= P4_SIBLING_SYS;  in p4_pcbe_configure()
862 			cfg->p4_escr |= ESCR_USR;  in p4_pcbe_configure()
864 			cfg->p4_escr |= ESCR_OS;  in p4_pcbe_configure()
867 	cfg->p4_rawpic = preset & MASK40;  in p4_pcbe_configure()
873 	cfg->p4_cccr = CCCR_INIT | (active_thread << CCCR_ACTV_THR_SHIFT);  in p4_pcbe_configure()
875 		cfg->p4_cccr |= CCCR_COMPARE;  in p4_pcbe_configure()
877 		cfg->p4_cccr |= CCCR_COMPLEMENT;  in p4_pcbe_configure()
878 	cfg->p4_cccr |= threshold << CCCR_THRESHOLD_SHIFT;  in p4_pcbe_configure()
880 		cfg->p4_cccr |= CCCR_EDGE;  in p4_pcbe_configure()
881 	cfg->p4_cccr |= p4_escrs[cfg->p4_escr_ndx].pe_num  in p4_pcbe_configure()
885 			cfg->p4_flags |= P4_PMI;  in p4_pcbe_configure()
896 			cfg->p4_cccr |= CCCR_OVF_PMI;  in p4_pcbe_configure()
900 	*data = cfg;  in p4_pcbe_configure()