680 #define	FERR_FAT_FSB_RD(fsb, ip)	((nb_chipset == INTEL_NB_7300) ? \  argument
683 #define	FERR_NF_FSB_RD(fsb, ip)	((nb_chipset == INTEL_NB_7300) ? \  argument
686 #define	NERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \  argument
689 #define	NERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \  argument
693 #define	NRECFSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
696 #define	NRECFSB_WR(fsb)	\  argument
703 #define	RECFSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
706 #define	RECFSB_WR(fsb) \  argument
713 #define	NRECADDR_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
719 #define	NRECADDR_WR(fsb) \  argument
729 #define	EMASK_FSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
732 #define	ERR0_FSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
735 #define	ERR1_FSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
738 #define	ERR2_FSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
741 #define	MCERR_FSB_RD(fsb)	((nb_chipset == INTEL_NB_7300) ? \  argument
754 #define	FERR_FAT_FSB_WR(fsb, val)	((nb_chipset == INTEL_NB_7300) ? \  argument
757 #define	FERR_NF_FSB_WR(fsb, val)	((nb_chipset == INTEL_NB_7300) ? \  argument
760 #define	NERR_FAT_FSB_WR(fsb, val)	((nb_chipset == INTEL_NB_7300) ? \  argument
763 #define	NERR_NF_FSB_WR(fsb, val)	((nb_chipset == INTEL_NB_7300) ? \  argument
766 #define	EMASK_FSB_WR(fsb, val) \  argument
774 #define	ERR0_FSB_WR(fsb, val) \  argument
782 #define	ERR1_FSB_WR(fsb, val) \  argument
790 #define	ERR2_FSB_WR(fsb, val) \  argument
798 #define	MCERR_FSB_WR(fsb, val) \  argument