1121 	    "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",  in ecpp_open()
1220 	ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",  in ecpp_close()
1559 		rg.dsr = DSR_READ(pp);  in ecpp_putioc()
1564 		ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",  in ecpp_putioc()
1565 		    rg.dsr, rg.dcr);  in ecpp_putioc()
1568 		rg.dsr |= ECPP_SETREGS_DSR_MASK;  in ecpp_putioc()
1734 		uint8_t	dsr;  in ecpp_putioc()  local
1739 		/* DSR only makes sense in Centronics & Compat mode */  in ecpp_putioc()
1742 			dsr = DSR_READ(pp);  in ecpp_putioc()
1743 			if ((dsr & ECPP_PE) ||  in ecpp_putioc()
1744 			    !(dsr & ECPP_SLCT) || !(dsr & ECPP_nERR)) {  in ecpp_putioc()
1760 		uint8_t	dsr;  in ecpp_putioc()  local
1773 		dsr = DSR_READ(pp);		/* read status */  in ecpp_putioc()
1777 		ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr);  in ecpp_putioc()
1779 		status = (dsr & (ECPP_SLCT | ECPP_PE | ECPP_nERR)) |  in ecpp_putioc()
1780 		    (~dsr & ECPP_nBUSY);  in ecpp_putioc()
3050 	uint8_t		dsr;  in ecpp_isr()  local
3055 	dsr = 0;  in ecpp_isr()
3114 	/* on 97317 in Extended mode IRQ_ST of DSR is deasserted when read */  in ecpp_isr()
3115 	dsr = DSR_READ(pp);  in ecpp_isr()
3120 	 * or in IRQ_ST bit of DSR on 97317  in ecpp_isr()
3127 		 * on Excalibur, reading DSR will deassert SuperIO IRQx line  in ecpp_isr()
3129 		 * so if DSR is read after interrupt occured, but before  in ecpp_isr()
3133 		 * malicious DSR reader is BPPIOC_TESTIO, which is called  in ecpp_isr()
3139 		if (((dsr & ECPP_IRQ_ST) == 0) ||  in ecpp_isr()
3141 		    (((dsr & ECPP_nERR) == 0) &&  in ecpp_isr()
3190 	if ((dsr & ECPP_nERR) == 0) {  in ecpp_isr()
3229 	    "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",  in ecpp_isr()
3230 	    dcsr, ECR_READ(pp), dsr, DCR_READ(pp),  in ecpp_isr()
3241 	    "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",  in ecpp_isr()
3289 	ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",  in ecpp_dma_ihdlr()
3500 			    "dsr=%x jl=%d cf_isr=%d\n",  in ecpp_softintr()
3978 	uint8_t	dsr;  in ecpp_check_status()  local
3987 	dsr = DSR_READ(pp);  in ecpp_check_status()
3988 	if ((dsr & ECPP_PE) || ((dsr & statmask) != statmask)) {  in ecpp_check_status()
4079 	/* status (DSR) only makes sense in Centronics & Compat modes */  in ecpp_get_prn_ifcap()
4158 	uint8_t dsr;  in ecp_negotiation()  local
4162 	if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE)  in ecp_negotiation()
4166 	if ((dsr & (ECPP_PE | ECPP_nBUSY | ECPP_SLCT)) !=  in ecp_negotiation()
4206 	uint8_t	dsr;  in nibble_negotiation()  local
4208 	if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) {  in nibble_negotiation()
4216 	if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {  in nibble_negotiation()
4259  * If rdsr is not NULL, DSR value after Event 6 is stored here
5222 	uint8_t dsr;  in devidnib_negotiation()  local
5225 	    ECPP_XREQ_NIBBLE | ECPP_XREQ_ID, &dsr) == FAILURE) {  in devidnib_negotiation()
5233 	if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {  in devidnib_negotiation()
5266 	uint8_t dsr;  in ecpp_getdevid()  local
5288 		dsr = DSR_READ(pp);  in ecpp_getdevid()
5296 			if ((dsr & ECPP_nERR) ||  in ecpp_getdevid()
5298 			    (dsr & ECPP_nERR) ||  in ecpp_getdevid()
5318 			while (i && ((dsr & ECPP_nERR) == 0)) {  in ecpp_getdevid()
5323 				dsr = DSR_READ(pp);  in ecpp_getdevid()
5910 	ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",  in m1553_config_chip()
5928 	ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",  in x86_config_chip()