Lines Matching refs:is_genregs
404 e = ddi_regs_map_setup(state->is_dip, 1, (caddr_t *)&state->is_genregs, in ioat_chip_init()
412 &state->is_genregs[IOAT_CHANCNT]); in ioat_chip_init()
423 &state->is_genregs[IOAT_XFERCAP]); in ioat_chip_init()
425 (uint16_t *)&state->is_genregs[IOAT_PERPORT_OFF]); in ioat_chip_init()
427 &state->is_genregs[IOAT_CBVER]); in ioat_chip_init()
429 (uint16_t *)&state->is_genregs[IOAT_INTRDELAY]); in ioat_chip_init()
431 (uint16_t *)&state->is_genregs[IOAT_CSSTATUS]); in ioat_chip_init()
433 (uint32_t *)&state->is_genregs[IOAT_DMACAPABILITY]); in ioat_chip_init()
593 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]); in ioat_intr_enable()
596 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS], in ioat_intr_enable()
601 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL], in ioat_intr_enable()
617 &state->is_genregs[IOAT_INTRCTL]); in ioat_intr_disable()
637 &state->is_genregs[IOAT_INTRCTL]); in ioat_isr()
645 &state->is_genregs[IOAT_INTRCTL], intrctrl); in ioat_isr()
651 (uint32_t *)&state->is_genregs[IOAT_ATTNSTATUS]); in ioat_isr()
671 ddi_put8(state->is_reg_handle, &state->is_genregs[IOAT_INTRCTL], in ioat_isr()