84  * hpet_state_lock is used to synchronize disabling/enabling deep c-states
102  * hpet_proxy_users is a per-cpu array.
116  * Set up pointers to access symbols in pcplusmp.
169 		 * ACPI, programming the interrupt on the non-legacy timer can  in hpet_early_init()
181 	 * the address of the first table while building up the boot  in hpet_early_init()
191 	if (BOP_GETPROPLEN(bootops, "hpet-table") != 8 ||  in hpet_early_init()
192 	    BOP_GETPROP(bootops, "hpet-table", (void *)&hpet_table) != 0) {  in hpet_early_init()
253 	 * the first available non-legacy replacement timer: timer 2.  in hpet_early_init()
284 	 * if it is used for more than just Deep C-State support.  in hpet_early_init()
286 	 * value before starting it for use to wake up CPUs from Deep C-States.  in hpet_early_init()
328  * Called by acpi_init() to set up HPET interrupts and fully initialize the
358 		 * If Deep C-States are disabled or not supported, then we do  in hpet_acpi_init()
386  * Do initial setup to use a HPET timer as a proxy for Deep C-state stalled
391  * ioapic_init_intr() in mp_platform_common() later sets up the I/O APIC
401 	if (hpet_get_IOAPIC_intr_capable_timer(&hpet_info) == -1) {  in hpet_init_proxy()
415 	hpet_flags->intr_el = INTR_EL_LEVEL;  in hpet_init_proxy()
416 	hpet_flags->intr_po = INTR_PO_ACTIVE_HIGH;  in hpet_init_proxy()
417 	hpet_flags->bustype = BUS_PCI;		/*  we *do* conform to PCI */  in hpet_init_proxy()
437  * Called by kernel if it can support Deep C-States.
469 	if (table_header->Length != sizeof (ACPI_TABLE_HPET)) {  in hpet_validate_table()
472 		    (unsigned long)((ACPI_TABLE_HEADER *)hpet_table)->Length,  in hpet_validate_table()
477 	if (!ACPI_COMPARE_NAME(table_header->Signature, ACPI_SIG_HPET)) {  in hpet_validate_table()
484 	    (unsigned int)table_header->Length)) {  in hpet_validate_table()
490 	 * Sequence should be table number - 1.  We are using table 1.  in hpet_validate_table()
492 	if (hpet_table->Sequence != HPET_TABLE_1 - 1) {  in hpet_validate_table()
494 		    (long)hpet_table->Sequence);  in hpet_validate_table()
516 	return (psm_map_new(hpet_table->Address.Address, (size_t)HPET_SIZE,  in hpet_memory_map()
526 	gcr_ptr = (uint64_t *)HPET_GEN_CONFIG_ADDRESS(hip->logical_address);  in hpet_start_main_counter()
542 	gcr_ptr = (uint64_t *)HPET_GEN_CONFIG_ADDRESS(hip->logical_address);  in hpet_stop_main_counter()
566  * This should be called before setting up timers.
595 	return (*(uint64_t *)HPET_GEN_CAP_ADDRESS(hip->logical_address));  in hpet_read_gen_cap()
602 	    HPET_GEN_CONFIG_ADDRESS(hip->logical_address));  in hpet_read_gen_config()
608 	hip->gen_intrpt_stat = *(uint64_t *)HPET_GEN_INTR_STAT_ADDRESS(  in hpet_read_gen_intrpt_stat()
609 	    hip->logical_address);  in hpet_read_gen_intrpt_stat()
610 	return (hip->gen_intrpt_stat);  in hpet_read_gen_intrpt_stat()
617 	    hip->logical_address, n);  in hpet_read_timer_N_config()
618 	hip->timer_n_config[n] = hpet_convert_timer_N_config(conf);  in hpet_read_timer_N_config()
649 	counter = (uint32_t *)HPET_MAIN_COUNTER_ADDRESS(hip->logical_address);  in hpet_read_main_counter_value()
652 	 * 32-bit main counters  in hpet_read_main_counter_value()
654 	if (hip->gen_cap.count_size_cap == 0) {  in hpet_read_main_counter_value()
656 		hip->main_counter_value = value;  in hpet_read_main_counter_value()
661 	 * HPET spec claims a 64-bit read can be split into two 32-bit reads  in hpet_read_main_counter_value()
672 	hip->main_counter_value = value;  in hpet_read_main_counter_value()
679 	*(uint64_t *)HPET_GEN_CONFIG_ADDRESS(hip->logical_address) = l;  in hpet_write_gen_config()
685 	*(uint64_t *)HPET_GEN_INTR_STAT_ADDRESS(hip->logical_address) = l;  in hpet_write_gen_intrpt_stat()
693 	 * capability; it is always a 64-bit value.  The top 32-bit half of  in hpet_write_timer_N_config()
694 	 * this register is always read-only so we constrain our write to the  in hpet_write_timer_N_config()
698 	    hip->logical_address, n);  in hpet_write_timer_N_config()
713 	*(uint64_t *)HPET_TIMER_N_COMP_ADDRESS(hip->logical_address, n) = l;  in hpet_write_timer_N_comp()
759  * Find the first available non-legacy-replacement timer and its I/O APIC irq.
770 	    timer < hip->gen_cap.num_tim_cap; ++timer) {  in hpet_get_IOAPIC_intr_capable_timer()
771 		if (!hpet_timer_available(hip->allocated_timers, timer))  in hpet_get_IOAPIC_intr_capable_timer()
774 		intr = lowbit(hip->timer_n_config[timer].int_route_cap) - 1;  in hpet_get_IOAPIC_intr_capable_timer()
780 			hpet_timer_alloc(&hip->allocated_timers, timer);  in hpet_get_IOAPIC_intr_capable_timer()
781 			hip->cstate_timer.timer = timer;  in hpet_get_IOAPIC_intr_capable_timer()
782 			hip->cstate_timer.intr = intr;  in hpet_get_IOAPIC_intr_capable_timer()
787 	return (-1);  in hpet_get_IOAPIC_intr_capable_timer()
855  * Writing a 64-bit value to a 32-bit register will "wrap around".
856  * A 32-bit HPET timer will wrap around in a little over 5 minutes.
875  * CPR and power policy-change callback entry point.
923  * not needed for Deep C-state wakeup when CPUs are in cpu_pause().
1019  * Callback to enable/disable Deep C-States based on power.conf setting.
1038 			ret = B_FALSE;  /* Deep C-States not supported */  in hpet_deep_idle_config()
1055 		 * proxy requests, then wake up all CPUs from deep C-state,  in hpet_deep_idle_config()
1056 		 * and finally disable the HPET interrupt-generating timer.  in hpet_deep_idle_config()
1097  * Callback for _CST c-state change notifications.
1141  * Interrupt Service Routine for HPET I/O-APIC-generated interrupts.
1142  * Used to wakeup CPUs from Deep C-state when their Local APIC Timer stops.
1143  * This ISR runs on one CPU which pokes other CPUs out of Deep C-state as
1157 	 * We are using a level-triggered interrupt.  in hpet_isr()
1178 	 * CPUs in deep c-states do not enable interrupts until after  in hpet_isr()
1183 	ASSERT(hpet_proxy_users[CPU->cpu_id] == HPET_INFINITY);  in hpet_isr()
1212  * Used when disabling the HPET Timer interrupt.  CPUs in Deep C-state must be
1213  * woken up because they can no longer rely on the HPET's Timer to wake them.
1224 			if (id != CPU->cpu_id)  in hpet_expire_all()
1256 		 * Wake all CPUs that expired before now.  in hpet_guaranteed_schedule()
1257 		 * Find the next CPU to wake up and next HPET program time.  in hpet_guaranteed_schedule()
1261 		next_proxy_id = CPU->cpu_id;  in hpet_guaranteed_schedule()
1265 				if (id != CPU->cpu_id)  in hpet_guaranteed_schedule()
1282 			 * A 64-bit timer will wrap around in ~ 2^44 seconds.  in hpet_guaranteed_schedule()
1283 			 * A 32-bit timer will wrap around in ~ 2^12 seconds.  in hpet_guaranteed_schedule()
1290 			 * deep c-state before the timer wraps around.  in hpet_guaranteed_schedule()
1294 			 * from deep c-state.  in hpet_guaranteed_schedule()
1302 			 * Deep C-State.  in hpet_guaranteed_schedule()
1305 			    HRTIME_TO_HPET_TICKS(next_proxy_time - gethrtime()))  in hpet_guaranteed_schedule()
1309 				 * next CPU.  We must wake the CPU ourself to  in hpet_guaranteed_schedule()
1313 				if (next_proxy_id != CPU->cpu_id)  in hpet_guaranteed_schedule()
1327  * Used in deep c-states C2 and above while the CPU's local APIC timer stalls.
1334  *	HPET		: not scheduled to wake this CPU
1339  *	HPET		: scheduled to wake this CPU
1344  *	HPET		: not scheduled to wake this CPU
1348  * The idle thread cannot enter Deep C-State in case 3.
1349  * The idle thread must re-enable & re-program the LAPIC_TIMER in case 2.
1358 	processorid_t	cpu_id = CPU->cpu_id;  in hpet_use_hpet_timer()
1363 	cpu_part = CPU->cpu_part;  in hpet_use_hpet_timer()
1364 	cpu_sid = CPU->cpu_seqid;  in hpet_use_hpet_timer()
1366 	ASSERT(CPU->cpu_thread == CPU->cpu_idle_thread);  in hpet_use_hpet_timer()
1383 	if (lapic_count == (hrtime_t)-1) {  in hpet_use_hpet_timer()
1406 			hset_update = (((CPU->cpu_flags & CPU_OFFLINE) == 0) &&  in hpet_use_hpet_timer()
1409 			    !bitset_in_set(&cpu_part->cp_haltset, cpu_sid)) {  in hpet_use_hpet_timer()
1418 		if (lapic_count == (hrtime_t)-1) {  in hpet_use_hpet_timer()
1473  * Called by the idle thread when waking up from Deep C-state before enabling
1479  * On a idle system the CPU was probably woken up by the HPET's ISR.
1480  * On a heavily loaded system CPUs are not going into Deep C-state.
1481  * On a moderately loaded system another CPU will usually enter Deep C-state
1487 	processorid_t	cpu_id = CPU->cpu_id;  in hpet_use_lapic_timer()
1489 	ASSERT(CPU->cpu_thread == CPU->cpu_idle_thread);  in hpet_use_lapic_timer()