Lines Matching +full:0 +full:x0010f000
34 #define TRC_GEN 0x0001f000 /* General trace */
35 #define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */
36 #define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */
37 #define TRC_HVM 0x0008f000 /* Xen HVM trace */
38 #define TRC_MEM 0x0010f000 /* Xen memory trace */
39 #define TRC_PV 0x0020f000 /* Xen PV traces */
40 #define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */
41 #define TRC_PM 0x0080f000 /* Xen power management trace */
42 #define TRC_ALL 0x0ffff000
43 #define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff)
52 #define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */
53 #define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */
55 #define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */
56 #define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */
97 #define TRC_64_FLAG (0x100)
116 #define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01)
117 #define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02)
118 #define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
119 #define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01)
120 #define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
121 #define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02)
122 #define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
123 #define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03)
124 #define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04)
125 #define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05)
126 #define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06)
127 #define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07)
128 #define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08)
129 #define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
130 #define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09)
131 #define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
132 #define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A)
133 #define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B)
134 #define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C)
135 #define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D)
136 #define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E)
137 #define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F)
138 #define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10)
139 #define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11)
140 #define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12)
141 #define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13)
142 #define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14)
143 #define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
144 #define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15)
145 #define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16)
146 #define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17)
147 #define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18)
148 #define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19)
149 #define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
150 #define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20)
151 #define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216)
152 #define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217)
155 #define TRC_PM_FREQ 0x00801000 /* xen cpu freq events */
156 #define TRC_PM_IDLE 0x00802000 /* xen cpu idle events */
159 #define TRC_PM_FREQ_CHANGE (TRC_PM_FREQ + 0x01)
160 #define TRC_PM_IDLE_ENTRY (TRC_PM_IDLE + 0x01)
161 #define TRC_PM_IDLE_EXIT (TRC_PM_IDLE + 0x02)
186 * 0 <= cons < 2*X
187 * 0 <= prod < 2*X