Lines Matching +full:prefetch +full:- +full:dma
47 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */
182 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */
209 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */
229 * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
235 * PCI Sub-class codes - base class 0x1 (mass storage controllers)
245 #define PCI_MASS_NVME 0x8 /* Non-Volatile memory controller */
261 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */
262 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */
278 * PCI Sub-class codes - base class 0x2 (Network controllers)
290 * PCI Sub-class codes - base class 03 (display controllers)
304 * PCI Sub-class codes - base class 0x4 (multi-media devices)
313 * PCI Sub-class codes - base class 0x5 (memory controllers)
320 * PCI Sub-class codes - base class 0x6 (Bridge devices)
330 #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */
331 #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */
337 * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge
339 #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */
351 * Semi-transparent PCI-to-PCI bridge
362 #define PCI_BRIDGE_AS_PORTAL_INTFC 0x1 /* ASI-SIG Portal Interface */
365 * PCI Sub-class codes - base class 0x7 (communication devices)
378 #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */
379 #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */
380 #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */
381 #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */
382 #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */
383 #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */
384 #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */
390 #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */
399 #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */
400 #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */
401 #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */
402 #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */
405 * PCI Sub-class codes - base class 0x8
408 #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */
411 #define PCI_PERIPH_HPC 0x4 /* Generic PCI Hot-Plug Controller */
426 * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller)
428 #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */
429 #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */
430 #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */
447 * PCI Sub-class codes - base class 0x9
463 * PCI Sub-class codes - base class 0xA
469 * PCI Sub-class codes - base class 0xB
477 #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */
481 * PCI Sub-class codes - base class 0xC (Serial Controllers)
518 * PCI Sub-class codes - base class 0xD (Wireless controllers)
536 * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
542 * PCI Sub-class codes - base class 0xF (Satellite Communication controllers)
551 * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers)
558 * PCI Sub-class codes - base class 0x11 (Signal Processing controllers)
568 #define PCI_HEADER_MULTI 0x80 /* multi-function device */
584 #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */
586 #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */
590 #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */
617 #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */
623 #define PCI_CAP_ID_P2P_SUBSYS 0xD /* PCI bridge Sub-system ID */
627 #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */
643 #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */
647 * PM capabilities values - 2 bytes
654 #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */
673 * PM control/status values - 2 bytes
699 * PM PMCSR PCI to PCI bridge support extension values - 1 byte
701 #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */
705 * PCI-X capability related definitions
715 * PCI-X bridge capability related definitions
771 * PCI-X Command Encoding
915 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit
918 #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */
919 #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */
920 #define PCI_MSI_32BIT_EXTDATA 0x0A /* MSI 32-bit msg ext data, 2 bytes */
921 #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */
922 #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */
925 * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit
927 #define PCI_MSI_64BIT_ADDR 0x08 /* MSI 64-bit upper address, 4 bytes */
928 #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */
929 #define PCI_MSI_64BIT_EXTDATA 0x0E /* MSI 64-bit msg ext data, 2 bytes */
930 #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */
931 #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */
947 * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets
949 #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */
950 #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */
951 #define PCI_MSIX_TBL_BIR_MASK 0x0007 /* MSI-X table BIR mask */
952 #define PCI_MSIX_PBA_OFFSET 0x08 /* MSI-X pending bit array, 4 bytes */
953 #define PCI_MSIX_PBA_BIR_MASK 0x0007 /* MSI-X PBA BIR mask */
955 #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */
956 #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */
957 #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */
959 #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */
960 #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */
961 #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */
962 #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */
963 #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */
969 #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */
985 * PCI_CAP_ID_HT. The header's upper 16-bits (command reg) contains an HT
1115 * property of a pci-pci bridge device node.
1130 * "assigned-addresses" property for a PCI node. For the "reg" property, it
1132 * windows. For the "assigned-addresses" property, it denotes an assigned
1147 * t is 1 if the address is aliased (for non-relocatable I/O), below
1150 * bbbbbbbb is the 8-bit bus number
1151 * ddddd is the 5-bit device number
1152 * fff is the 3-bit function number
1153 * rrrrrrrr is the 8-bit register number
1154 * should be zero for non-relocatable, when ss is 01, or 10
1155 * hh...hhh is the 32-bit unsigned number
1156 * ll...lll is the 32-bit unsigned number
1163 * hh...hhh is the 32-bit unsigned number
1164 * ll...lll is the 32-bit unsigned number
1185 #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */
1214 #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */
1215 #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */
1217 #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */
1218 #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */
1221 #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */
1222 #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */
1223 #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */
1252 #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */
1260 #define PCI_DEV_CONF_MAP_PROP "pci-parent-indirect"
1268 #define PCI_BUS_CONF_MAP_PROP "pci-conf-indirect"