Lines Matching defs:ibt_hca_attr_s
435 typedef struct ibt_hca_attr_s { struct
436 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */
437 ibt_hca_flags2_t hca_flags2;
440 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */
441 uint16_t hca_device_id;
442 uint32_t hca_version_id;
444 uint_t hca_max_chans; /* Max Chans supported */
445 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */
448 uint_t hca_max_sgl; /* Max SGL entries per WR */
450 uint_t hca_max_cq; /* Max num of CQs supported */
451 uint_t hca_max_cq_sz; /* Max capacity of each CQ */
453 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */
455 uint_t hca_max_memr; /* Max num of HCA mem regions */
456 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */
458 uint_t hca_max_mem_win; /* Max Memory windows in HCA */
460 uint_t hca_max_rsc; /* Max Responder Resources of */
463 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */
465 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */
467 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */
468 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */
470 uint_t hca_max_mcg_chans; /* Max number of channels */
473 uint_t hca_max_mcg; /* Max multicast groups */
474 uint_t hca_max_chan_per_mcg; /* Max number of channels per */
477 uint16_t hca_max_partitions; /* Max partitions in HCA */
478 uint8_t hca_nports; /* Number of physical ports */
479 ib_guid_t hca_node_guid; /* Node GUID */
481 ib_time_t hca_local_ack_delay;
483 uint_t hca_max_port_sgid_tbl_sz;
484 uint16_t hca_max_port_pkey_tbl_sz;
485 uint_t hca_max_pd; /* Max# of Protection Domains */
486 ib_guid_t hca_si_guid; /* Optional System Image GUID */
487 uint_t hca_hca_max_ci_priv_sz;
488 uint_t hca_chan_max_ci_priv_sz;
489 uint_t hca_cq_max_ci_priv_sz;
490 uint_t hca_pd_max_ci_priv_sz;
491 uint_t hca_mr_max_ci_priv_sz;
492 uint_t hca_mw_max_ci_priv_sz;
493 uint_t hca_ud_dest_max_ci_priv_sz;
494 uint_t hca_cq_sched_max_ci_priv_sz;
495 uint_t hca_max_ud_dest;
496 uint_t hca_opaque2;
497 uint_t hca_opaque3;
498 uint_t hca_opaque4;
499 uint8_t hca_opaque5;
500 uint8_t hca_opaque6;
501 uint8_t hca_rss_max_log2_table; /* max RSS log2 table size */
502 uint_t hca_opaque7;
503 uint_t hca_opaque8;
504 uint_t hca_max_srqs; /* Max SRQs supported */
505 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */
507 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */
508 uint_t hca_max_phys_buf_list_sz;
509 size_t hca_block_sz_lo; /* Range of block sizes */
510 size_t hca_block_sz_hi; /* supported by the HCA */
511 uint_t hca_max_cq_handlers;
512 ibt_lkey_t hca_reserved_lkey; /* Reserved L_Key value */
513 uint_t hca_max_fmrs; /* Max FMR Supported */
514 uint_t hca_opaque9;
516 uint_t hca_max_lso_size;
517 uint_t hca_max_lso_hdr_size;
518 uint_t hca_max_inline_size;
520 uint_t hca_max_cq_mod_count; /* CQ notify moderation */
521 uint_t hca_max_cq_mod_usec;
523 uint32_t hca_fw_major_version; /* firmware version */
524 uint16_t hca_fw_minor_version;
525 uint16_t hca_fw_micro_version;
527 uint_t hca_max_xrc_domains; /* XRC items */
528 uint_t hca_max_xrc_srqs;
529 uint_t hca_max_xrc_srq_size;
530 uint_t hca_max_xrc_srq_sgl;
533 uint_t hca_ud_send_inline_sz; /* inline size in bytes */
534 uint_t hca_conn_send_inline_sz;
535 uint_t hca_conn_rdmaw_inline_overhead;
536 uint_t hca_recv_sgl_sz; /* detailed SGL sizes */
537 uint_t hca_ud_send_sgl_sz;
538 uint_t hca_conn_send_sgl_sz;
539 uint_t hca_conn_rdma_read_sgl_sz;
540 uint_t hca_conn_rdma_write_sgl_sz;
541 uint_t hca_conn_rdma_sgl_overhead;
544 uint8_t hca_rfci_max_log2_qp; /* max log2 RFCI QPs */
545 uint8_t hca_fexch_max_log2_qp; /* max log2 FEXCH QPs */
546 uint8_t hca_fexch_max_log2_mem; /* max log2 mem per FEXCH */
548 dev_info_t *hca_dip; /* HCA dev_info */