Lines Matching full:dmac

65 /* NSC 87332/97317 and EBus DMAC */
69 	struct cheerio_dma_reg	*dmac;		/* ebus dmac registers */  member
70 	ddi_acc_handle_t	d_handle;	/* handle for dmac registers */
75 /* Southbridge SuperIO and 8237 DMAC */
327 #define	ECPP_ISR_MAX_DELAY	30	/* DMAC slow PENDING status */
478  * Macros for Cheerio/RIO DMAC programming
481 				((uint32_t *)&pp->uh.ebus.dmac->csr), \
484 				(uint32_t *)&(pp->uh.ebus.dmac->csr))
487 				((uint32_t *)&pp->uh.ebus.dmac->acr), \
491 				(uint32_t *)&pp->uh.ebus.dmac->acr)
494 				((uint32_t *)&pp->uh.ebus.dmac->bcr), \
498 				((uint32_t *)&pp->uh.ebus.dmac->bcr))