Lines Matching +full:rx +full:- +full:ctrl
12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
129 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Adv. Error Cap./Ctrl */
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
137 #define PCI_Y2_PHY2_POWD BIT(27) /* Set PHY 2 to Power Down (YUKON-2) */
138 #define PCI_Y2_PHY1_POWD BIT(26) /* Set PHY 1 to Power Down (YUKON-2) */
150 #define PCI_PEX_LEGNAT BIT(15) /* PEX PM legacy/native (YUKON-2) */
158 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
159 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
160 #define PCI_CLS_OPT BIT(3) /* Cache Line Size PCI-X (YUKON-2) */
181 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
183 #define PCI_OS_PCIX BIT(30) /* PCI-X Bus */
184 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
186 #define PCI_OS_PCI_X BIT(26) /* PCI/PCI-X Bus (0 = PEX) */
191 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Spd */
194 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
195 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
196 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
198 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
211 /* PCI_OUR_REG_5 - 32 bit Our Register 5 (Yukon-ECU only) */
215 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
225 #define PEX_DC_EN_NFA_ER_RP BIT(1) /* Enable Non-Fatal Error Report */
230 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
237 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
265 /* Special ISR registers (Yukon-2 only) */
274 * - completely empty (this is the RAP Block window)
290 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
291 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
323 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
326 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
328 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
349 * Bank 4 - 5
362 /* RSS key registers for Yukon-2 Family */
363 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
369 /* 0x0280 - 0x0292: MAC 2 */
374 * Bank 8 - 15
425 * Bank 16 - 23
435 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
436 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
437 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
438 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
448 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
449 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
450 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
451 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
452 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
453 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
454 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
455 #define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
456 #define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
457 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
458 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
459 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
460 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
461 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
466 /* 0x0c80 - 0x0cbf: MAC 2 */
467 /* 0x0cc0 - 0x0cff: reserved */
472 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
477 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
488 /* 0x0d80 - 0x0dbf: MAC 2 */
489 /* 0x0daa - 0x0dff: reserved */
497 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
501 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
503 /* Polling Unit Registers (Yukon-2 only) */
508 /* ASF Subsystem Registers (Yukon-2 only) */
523 /* Status BMU Registers (Yukon-2 only) */
534 /* FIFO Control/Status Registers (Yukon-2 only) */
542 /* Level and ISR Timer Registers (Yukon-2 only) */
571 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
573 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
580 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
581 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
595 * Bank 32 - 33
600 /* offset to configuration space on Yukon-2 */
611 #define Y2_VMAIN_AVAIL BIT(17) /* VMAIN available (YUKON-2 only) */
612 #define Y2_VAUX_AVAIL BIT(16) /* VAUX available (YUKON-2 only) */
613 #define Y2_HW_WOL_ON BIT(15) /* HW WOL On (Yukon-EC Ultra A1 only) */
614 #define Y2_HW_WOL_OFF BIT(14) /* HW WOL Off (Yukon-EC Ultra A1 only) */
615 #define Y2_ASF_ENABLE BIT(13) /* ASF Unit Enable (YUKON-2 only) */
616 #define Y2_ASF_DISABLE BIT(12) /* ASF Unit Disable (YUKON-2 only) */
617 #define Y2_CLK_RUN_ENA BIT(11) /* CLK_RUN Enable (YUKON-2 only) */
618 #define Y2_CLK_RUN_DIS BIT(10) /* CLK_RUN Disable (YUKON-2 only) */
619 #define Y2_LED_STAT_ON BIT(9) /* Status LED On (YUKON-2 only) */
620 #define Y2_LED_STAT_OFF BIT(8) /* Status LED Off (YUKON-2 only) */
661 #define Y2_IS_CHK_RX2 BIT(10) /* Descriptor error Rx 2 */
666 #define Y2_IS_CHK_RX1 BIT(2) /* Descriptor error Rx 1 */
686 #define Y2_IS_PCI_EXP BIT(25) /* PCI-Express interrupt */
687 #define Y2_IS_PCI_NEXP BIT(24) /* PCI-Express error similar to PCI error */
691 #define Y2_IS_PAR_RX2 BIT(10) /* Parity Error Rx Queue 2 */
697 #define Y2_IS_PAR_RX1 BIT(2) /* Parity Error Rx Queue 1 */
718 * as they are pre-yukon 2 chips
722 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
723 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
725 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
726 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
727 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
728 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
729 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
730 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
731 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
732 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
735 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
736 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
738 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
739 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
740 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
741 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
743 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
744 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
745 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
747 #define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
748 #define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
749 #define CHIP_REV_YU_EC_U_B0 3 /* Chip Rev. for Yukon-EC Ultra B0 */
750 #define CHIP_REV_YU_EC_U_B1 5 /* Chip Rev. for Yukon-EC Ultra B1 */
751 #define CHIP_REV_YU_FE_A1 1 /* Chip Rev. for Yukon-FE A1 */
752 #define CHIP_REV_YU_FE_A2 3 /* Chip Rev. for Yukon-FE A2 */
753 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-Extreme A0 */
754 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-Extreme B0 */
756 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-Supreme A0 */
757 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-Supreme B0 */
758 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-Supreme B1 */
762 /* B2_Y2_CLK_GATE - 8 bit Clock Gating (Yukon-2 only) */
772 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
783 /* B2_Y2_CLK_CTRL 32 bit Core Clck Frqncy Control Rgstr (Yukon-2/EC) */
784 /* Yukon-EC/FE */
787 /* Yukon-2 */
812 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
883 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
930 /* Rx BMU Control / Status Registers (Yukon-2) */
932 #define BMU_RX_TCP_PKT BIT(30) /* Rx TCP Packet (when RSS Hash enab) */
933 #define BMU_RX_IP_PKT BIT(29) /* Rx IP Packet (when RSS Hash enab) */
934 #define BMU_ENA_RX_RSS_HASH BIT(15) /* Enable Rx RSS Hash */
935 #define BMU_DIS_RX_RSS_HASH BIT(14) /* Disable Rx RSS Hash */
936 #define BMU_ENA_RX_CHKSUM BIT(13) /* Enable Rx TCP/IP Checksum Check */
937 #define BMU_DIS_RX_CHKSUM BIT(12) /* Disable Rx TCP/IP Checksum Check */
938 #define BMU_CLR_IRQ_PAR BIT(11) /* Clear IRQ on Parity errors (Rx) */
941 #define BMU_STOP BIT(9) /* Stop Rx/Tx Queue */
942 #define BMU_START BIT(8) /* Start Rx/Tx Queue */
956 /* Tx BMU Control / Status Registers (Yukon-2) */
957 /* Bit 31: same as for Rx */
961 /* Bit 10..0: same as for Rx */
964 #define F_TX_CHK_AUTO_OFF BIT(31) /* Tx csum auto-calc Off (Yukon EX) */
965 #define F_TX_CHK_AUTO_ON BIT(30) /* Tx csum auto-calc On (Yukon EX) */
966 #define F_ALM_FULL BIT(27) /* Rx FIFO: almost full */
970 #define F_M_RX_RAM_DIS BIT(24) /* MAC Rx RAM Read Port disable */
974 /* Queue Prefetch Unt Offsts, use Y2_PREF_Q_ADDR() to addrss (Yukon-2 only) */
986 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
987 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
988 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
989 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1021 /* Threshold values for Yukon-EC Ultra */
1031 #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
1034 #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
1044 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
1045 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1051 /* Minimum RAM Buffer Rx Queue Size */
1087 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1093 * Marvell-PHY Registers, indirect addressed over GMAC
1095 /* Marvell-specific registers */
1096 /* 0x0b - 0x0e: reserved */
1108 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Spec. Ctrl 2 */
1119 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Ctrl Reg. 2 */
1123 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1124 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1125 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1126 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1127 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1130 /* PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg */
1132 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1153 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1174 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1190 #define PHY_M_PS_RX_P_EN BIT(2) /* Rx Pause Enabled */
1202 #define PHY_M_IS_AN_ERROR BIT(15) /* Auto-Negotiation Error */
1206 #define PHY_M_IS_AN_COMPL BIT(11) /* Auto-Negotiation Completed */
1223 /* PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl */
1235 #define PHY_M_EC_RX_TIM_CT BIT(7) /* RGMII Rx Timing Control */
1237 #define PHY_M_EC_FIB_AN_ENA BIT(3) /* Fbr Aut-Neg. Enbl (88E1011S only) */
1269 #define PHY_M_LEDC_RX_CTRL BIT(1) /* Rx Activity / Link */
1298 #define PHY_M_LED_MO_RX(x) (x << 2) /* Bit 3.. 2: Rx */
1306 /* PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 */
1370 #define PHY_M_FESC_ENA_MCLK BIT(1) /* Enable MAC Rx Clock in sleep mode */
1371 #define PHY_M_FESC_SEL_CL_A BIT(0) /* Select Class A driver (100B-TX) */
1373 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1374 /* PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl */
1379 /* PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl */
1382 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1384 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1388 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1389 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1390 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Msk */
1391 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1401 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Msk */
1402 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Msk */
1403 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Msk */
1404 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Msk */
1428 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1448 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1449 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1453 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1454 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1466 * MIB Counters base address definitions (low word) -
1471 #define GM_RXF_MPAUSE (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Rx'd */
1473 #define GM_RXF_FCS_ERR (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
1474 #define GM_RXF_SPARE1 (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */
1479 #define GM_RXF_SHT (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte RX OK */
1480 #define GM_RXE_FRAG (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte RX FCS Err */
1481 #define GM_RXF_64B (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */
1482 #define GM_RXF_127B (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1483 #define GM_RXF_255B (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1484 #define GM_RXF_511B (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1485 #define GM_RXF_1023B (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1486 #define GM_RXF_1518B (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1487 #define GM_RXF_MAX_SZ (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1488 #define GM_RXF_LNG_ERR (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
1489 #define GM_RXF_JAB_PKT (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
1490 #define GM_RXF_SPARE2 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */
1491 #define GM_RXE_FIFO_OV (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
1492 #define GM_RXF_SPARE3 (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */
1495 #define GM_TXF_MPAUSE (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames TX */
1500 #define GM_TXF_127B (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1501 #define GM_TXF_255B (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1502 #define GM_TXF_511B (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1503 #define GM_TXF_1023B (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1504 #define GM_TXF_1518B (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1505 #define GM_TXF_MAX_SZ (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1527 #define GM_GPSR_FC_TX_DIS BIT(13) /* Tx Flow-Control Mode Disabled */
1536 #define GM_GPSR_FC_RX_DIS BIT(2) /* Rx Flow-Control Mode Disabled */
1539 #define GM_GPCR_RMII_PH_ENA BIT(15) /* Enbl RMII for PHY (Yukon-FE only) */
1540 #define GM_GPCR_RMII_LB_ENA BIT(14) /* Enable RMII Lpbck (Yukon-FE only) */
1541 #define GM_GPCR_FC_TX_DIS BIT(13) /* Disable Tx Flow-Control Mode */
1549 #define GM_GPCR_FC_RX_DIS BIT(4) /* Disable Rx Flow-Control Mode */
1551 #define GM_GPCR_AU_DUP_DIS BIT(2) /* Disable Auto-Update Duplex */
1552 #define GM_GPCR_AU_FCT_DIS BIT(1) /* Disable Auto-Update Flow-C. */
1553 #define GM_GPCR_AU_SPD_DIS BIT(0) /* Disable Auto-Update Speed */
1560 #define GM_TXCR_FORCE_JAM BIT(15) /* Force Jam / Flow-Control */
1565 /* (Yukon-2 only) */
1573 #define GM_RXCR_CRC_DIS BIT(13) /* Remove 4-byte CRC */
1574 #define GM_RXCR_PASS_FC BIT(12) /* Pass FC pckts FIFO (Yukon-1 only) */
1581 /* (Yukon-2 only) */
1595 /* r/o on Yukon, r/w on Yukon-EC */
1599 #define GM_NEW_FLOW_CTRL BIT(6) /* Enable New Flow-Control */
1600 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Intr-Pckt Gap (IPG) */
1623 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1630 #define GMR_FS_GOOD_FC BIT(7) /* Good Flow-Control Packet */
1631 #define GMR_FS_BAD_FC BIT(6) /* Bad Flow-Control Packet */
1636 #define GMR_FS_RX_FF_OV BIT(0) /* Rx FIFO Overflow */
1651 /* Rx GMAC FIFO Flush Mask (default) */
1656 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1657 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1658 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1659 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1660 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1661 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1671 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1684 #define GMF_RX_F_FL_ON BIT(7) /* Rx FIFO Flush Mode On */
1685 #define GMF_RX_F_FL_OFF BIT(6) /* Rx FIFO Flush Mode Off */
1686 #define GMF_CLI_RX_FO BIT(5) /* Clear IRQ Rx FIFO Overrun */
1687 #define GMF_CLI_RX_FC BIT(4) /* Clear IRQ Rx Frame Complete */
1693 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1694 #define TX_STFW_DIS BIT(31) /* Disable Store & Forward (Yukon-EC Ultra) */
1695 #define TX_STFW_ENA BIT(30) /* Enable Store & Forward (Yukon-EC Ultra) */
1698 #define TX_JUMBO_ENA BIT(23) /* Enable Jumbo Mode (Yukon-EC Ultra) */
1699 #define TX_JUMBO_DIS BIT(22) /* Disable Jumbo Mode (Yukon-EC Ultra) */
1712 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almst Full Thrsh. min. */
1713 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
1715 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1720 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
1747 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1757 #define GMC_BYP_MACSECRX_ON BIT(13) /* Bypass macsec RX */
1758 #define GMC_BYP_MACSECRX_OFF BIT(12) /* Bypass macsec RX off */
1773 #define GPC_SEL_BDT BIT(28) /* Select Bi-Dir. Transfer for MDC/MDIO */
1817 ddi_put32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)), (v))
1819 ddi_put16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)), (v))
1821 ddi_put8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)), (v))
1824 ddi_get32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)))
1826 ddi_get16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)))
1828 ddi_get8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)))
1839 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
1852 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status))
1855 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status))
1858 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_control))
1861 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status, v))
1864 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status, v))
1867 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_control, v))
1870 (void) ddi_dma_sync((ring)->r_dmah, (i) * sizeof (yge_desc_t), \
1874 bzero((ring)->r_kaddr, (ring)->r_size)
1877 (void) ddi_dma_sync((ring)->r_dmah, 0, 0, (flags))
1880 (void) ddi_dma_sync(b->b_dmah, 0, 0, flags)
1942 /* YUKON-2 bit values */
1948 /* YUKON-2 Control flags */
1965 /* YUKON-2 Rx/Tx opcodes defines */
1984 /* YUKON-2 STATUS opcodes defines */
1994 /* YUKON-2 SPECIAL opcodes defines */
2013 #define BMU_DEV_0 BIT(26) /* (Rx) Transfer data to Dev0 */
2014 #define BMU_STAT_VAL BIT(25) /* (Rx) Rx Status Valid */
2015 #define BMU_TIST_VAL BIT(24) /* (Rx) Rx TimeStamp Valid */
2056 /* Note: We could conceivably change this to support 64-bit */
2068 #define YGE_PROC_MAX (YGE_RX_RING_CNT - 1)
2074 /* Rx stats. */
2185 * RX lock protects receive resources, status ring, hardware
2198 * All of these locks are shaerd between both ports on a multi-port device.
2207 #define RX_LOCK(dev) mutex_enter(&dev->d_rxlock);
2208 #define RX_UNLOCK(dev) mutex_exit(&dev->d_rxlock);
2209 #define TX_LOCK(dev) mutex_enter(&dev->d_txlock);
2210 #define TX_UNLOCK(dev) mutex_exit(&dev->d_txlock);
2211 #define PHY_LOCK(dev) mutex_enter(&dev->d_phylock);
2212 #define PHY_UNLOCK(dev) mutex_exit(&dev->d_phylock);
2224 #define TASK_LOCK(dev) mutex_enter(&(dev)->d_task_mtx)
2225 #define TASK_UNLOCK(dev) mutex_exit(&(dev)->d_task_mtx)
2226 #define TASK_WAIT(dev) cv_wait(&(dev)->d_task_cv, &(dev)->d_task_mtx)
2227 #define TASK_SIGNAL(dev) cv_signal(&(dev)->d_task_cv)
2229 #define YGE_USECS(sc, us) ((sc)->d_clock * (us))
2249 uint32_t p_rxq; /* Rx. Qeueue offset */
2286 (((dev)->d_Features[((ReqFeature) & 0x30000000UL) >> 28] &\
2295 #define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */
2303 #define HWF_NEW_FLOW_CONTROL 0x00040000UL /* New Flow-Control support */
2309 #define HWF_WA_DEV_56 0x14000000UL /* 5.6 (Rx Chksum 0xffff) */
2313 #define HWF_WA_DEV_4217 0x10400000UL /* 4.217 (PCI-E blockage) */
2317 #define HWF_WA_DEV_4167 0x10040000UL /* 4.167 (Rx OvSize Hang) */
2319 #define HWF_WA_DEV_4115 0x10010000UL /* 4.115 (Rx MAC FIFO) */
2321 #define HWF_WA_DEV_483 0x10004000UL /* 4.83 (Rx TCP wrong) */
2322 #define HWF_WA_DEV_479 0x10002000UL /* 4.79 (Rx BMU hang II) */
2324 #define HWF_WA_DEV_463 0x10000800UL /* 4.63 (Rx BMU hang I) */
2335 #define HWF_WA_DEV_428 0x10000004UL /* 4.28 (Poll-U &BigEndi) */
2336 #define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /* dis Rx GMAC FIFO Flush */
2337 /* for Yu-L Rev. A0 only */