Lines Matching full:gmac
448 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
449 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
450 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
451 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
452 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
453 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
458 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
459 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
460 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
461 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
472 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
474 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
475 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
476 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
478 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
479 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
480 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
481 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
482 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
483 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
564 /* GMAC and GPHY Control Registers (YUKON only) */
565 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
567 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
568 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
604 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */
605 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
1093 * Marvell-PHY Registers, indirect addressed over GMAC
1414 * GMAC registers
1416 * The GMAC registers are 16 or 32 bits wide.
1515 * GMAC Bit Definitions
1651 /* Rx GMAC FIFO Flush Mask (default) */
1654 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
1656 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1657 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1658 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1659 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1660 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1661 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1662 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1663 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh. */
1664 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1665 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1666 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1667 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1668 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1669 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1671 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1690 #define GMF_RST_CLR BIT(1) /* Clear GMAC FIFO Reset */
1691 #define GMF_RST_SET BIT(0) /* Set GMAC FIFO Reset */
1693 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1712 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almst Full Thrsh. min. */
1713 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
1754 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1769 #define GMC_RST_CLR BIT(1) /* Clear GMAC Reset */
1770 #define GMC_RST_SET BIT(0) /* Set GMAC Reset */
1797 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1798 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1808 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1809 #define GMLC_RST_CLR BIT(1) /* Clear GMAC Link Reset */
1810 #define GMLC_RST_SET BIT(0) /* Set GMAC Link Reset */
2336 #define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /* dis Rx GMAC FIFO Flush */