Lines Matching +full:16 +full:- +full:bit
12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
97 #define BIT(n) (1U << n) macro
102 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
103 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
104 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
105 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
106 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
107 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
108 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
109 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
112 #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
113 #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
114 #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
115 #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
116 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
117 #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
118 #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
119 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
120 #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
123 #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
124 #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
125 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
126 #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
127 #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
128 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
129 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Adv. Error Cap./Ctrl */
130 #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
132 /* PCI_OUR_REG_1 32 bit Our Register 1 */
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
137 #define PCI_Y2_PHY2_POWD BIT(27) /* Set PHY 2 to Power Down (YUKON-2) */
138 #define PCI_Y2_PHY1_POWD BIT(26) /* Set PHY 1 to Power Down (YUKON-2) */
139 #define PCI_DIS_BOOT BIT(24) /* Disable BOOT via ROM */
140 #define PCI_EN_IO BIT(23) /* Mapping to I/O space */
141 #define PCI_EN_FPROM BIT(22) /* Enable FLASH mapping to memory */
144 #define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
145 #define PCI_PAGE_16 (0L<<20) /* 16 k pages */
149 #define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
150 #define PCI_PEX_LEGNAT BIT(15) /* PEX PM legacy/native (YUKON-2) */
151 #define PCI_FORCE_BE BIT(14) /* Assert all BEs on MR */
152 #define PCI_DIS_MRL BIT(13) /* Disable Mem Read Line */
153 #define PCI_DIS_MRM BIT(12) /* Disable Mem Read Multiple */
154 #define PCI_DIS_MWI BIT(11) /* Disable Mem Write & Invalidate */
155 #define PCI_DISC_CLS BIT(10) /* Disc: cacheLsz bound */
156 #define PCI_BURST_DIS BIT(9) /* Burst Disable */
157 #define PCI_DIS_PCI_CLK BIT(8) /* Disable PCI clock driving */
158 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
159 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
160 #define PCI_CLS_OPT BIT(3) /* Cache Line Size PCI-X (YUKON-2) */
162 /* PCI_OUR_REG_2 32 bit Our Register 2 */
163 #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */
164 #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */
165 #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */
166 /* Bit 13..12: reserved */
167 #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
168 #define PCI_PATCH_DIR_3 BIT(11)
169 #define PCI_PATCH_DIR_2 BIT(10)
170 #define PCI_PATCH_DIR_1 BIT(9)
171 #define PCI_PATCH_DIR_0 BIT(8)
172 #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */
173 #define PCI_EXT_PATCH_3 BIT(7)
174 #define PCI_EXT_PATCH_2 BIT(6)
175 #define PCI_EXT_PATCH_1 BIT(5)
176 #define PCI_EXT_PATCH_0 BIT(4)
177 #define PCI_EN_DUMMY_RD BIT(3) /* Enable Dummy Read */
178 #define PCI_REV_DESC BIT(2) /* Reverse Desc. Bytes */
179 #define PCI_USEDATA64 BIT(0) /* Use 64Bit Data bus ext */
181 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
182 #define PCI_OS_PCI64B BIT(31) /* Conventional PCI 64 bits Bus */
183 #define PCI_OS_PCIX BIT(30) /* PCI-X Bus */
184 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
185 #define PCI_OS_PCI66M BIT(27) /* PCI 66 MHz Bus */
186 #define PCI_OS_PCI_X BIT(26) /* PCI/PCI-X Bus (0 = PEX) */
187 #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */
188 #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Cntrs Values */
189 #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Cntrs Values */
191 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Spd */
194 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
195 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
196 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
198 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
199 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Tmr Vul Msk */
200 #define PCI_FORCE_ASPM_REQUEST BIT(15) /* Force ASPM Request (A1 only) */
201 #define PCI_ASPM_GPHY_LINK_DOWN BIT(14) /* GPHY Link Down (A1 only) */
202 #define PCI_ASPM_INT_FIFO_EMPTY BIT(13) /* Internal FIFO Empty (A1 only) */
203 #define PCI_ASPM_CLKRUN_REQUEST BIT(12) /* CLKRUN Request (A1 only) */
204 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT(4) /* Frc CLKRQ Enbl (A1b only) */
205 #define PCI_ASPM_CLKREQ_PAD_CTL BIT(3) /* CLKREQ PAD Control (A1 only) */
206 #define PCI_ASPM_A1_MODE_SELECT BIT(2) /* A1 Mode Select (A1 only) */
207 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT(1) /* Enable Gate PEX Unit Clock */
208 #define PCI_CLK_GATE_ROOT_COR_ENA BIT(0) /* Enbl Gate Root Core Clock */
211 /* PCI_OUR_REG_5 - 32 bit Our Register 5 (Yukon-ECU only) */
212 /* Bit 31..27: for A3 & later */
213 #define P_CTL_TIM_VMAIN_AV_MSK (3<<27) /* Bit 28..27: Timer Vmain_av Mask */
215 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
216 #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request */
217 #define PEX_DC_EN_NO_SNOOP BIT(11) /* Enable No Snoop */
218 #define PEX_DC_EN_AUX_POW BIT(10) /* Enable AUX Power */
219 #define PEX_DC_EN_PHANTOM BIT(9) /* Enable Phantom Functions */
220 #define PEX_DC_EN_EXT_TAG BIT(8) /* Enable Extended Tag Field */
221 #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size */
222 #define PEX_DC_EN_REL_ORD BIT(4) /* Enable Relaxed Ordering */
223 #define PEX_DC_EN_UNS_RQ_RP BIT(3) /* Enable Unsupported Request Report */
224 #define PEX_DC_EN_FAT_ER_RP BIT(2) /* Enable Fatal Error Report */
225 #define PEX_DC_EN_NFA_ER_RP BIT(1) /* Enable Non-Fatal Error Report */
226 #define PEX_DC_EN_COR_ER_RP BIT(0) /* Enable Correctable Error Report */
230 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
231 #define PEX_LS_SLOT_CLK_CFG BIT(12) /* Slot Clock Config */
232 #define PEX_LS_LINK_TRAIN BIT(11) /* Link Training */
233 #define PEX_LS_TRAIN_ERROR BIT(10) /* Training Error */
234 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width */
235 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
237 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
238 #define PEX_UNSUP_REQ BIT(20) /* Unsupported Request Error */
239 #define PEX_MALFOR_TLP BIT(18) /* Malformed TLP */
240 #define PEX_RX_OV BIT(17) /* Receiver Overflow (not supported) */
241 #define PEX_UNEXP_COMP BIT(16) /* Unexpected Completion */
242 #define PEX_COMP_TO BIT(14) /* Completion Timeout */
243 #define PEX_FLOW_CTRL_P BIT(13) /* Flow Control Protocol Error */
244 #define PEX_POIS_TLP BIT(12) /* Poisoned TLP */
245 #define PEX_DATA_LINK_P BIT(4) /* Data Link Protocol Error */
255 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
256 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
257 #define B0_LED 0x0006 /* 8 Bit LED register */
258 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
259 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
260 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
261 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
262 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
263 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
265 /* Special ISR registers (Yukon-2 only) */
266 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
267 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
268 #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */
269 #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */
270 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
274 * - completely empty (this is the RAP Block window)
281 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
285 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
286 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
287 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
288 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
289 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
290 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
291 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
292 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
293 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
294 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */
295 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */
296 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
297 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
298 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg. */
299 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
300 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
301 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
302 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
303 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
304 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
305 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
306 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */
307 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
308 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
309 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
310 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
312 #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
313 #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
319 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
320 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
321 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
323 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
326 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
328 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
332 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */
333 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
334 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
335 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
336 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
337 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
338 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
339 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
340 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
341 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
342 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10) */
343 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11) */
344 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */
345 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
346 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */
349 * Bank 4 - 5
352 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val */
353 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
354 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
355 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
356 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
357 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
358 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
362 /* RSS key registers for Yukon-2 Family */
363 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
369 /* 0x0280 - 0x0292: MAC 2 */
374 * Bank 8 - 15
380 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
381 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
382 #define Q_DONE 0x24 /* 16 bit Done Index */
383 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
384 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
385 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
386 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
387 #define Q_F 0x38 /* 32 bit Flag Register */
388 #define Q_T1 0x3c /* 32 bit Test Register 1 */
389 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
390 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
391 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
392 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
393 #define Q_WM 0x40 /* 16 bit FIFO Watermark */
394 #define Q_AL 0x42 /* 8 bit FIFO Alignment */
395 #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
396 #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
397 #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */
398 #define Q_RL 0x4a /* 8 bit FIFO Read Level */
399 #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */
400 #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
401 #define Q_WL 0x4e /* 8 bit FIFO Write Level */
402 #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
409 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
410 #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
411 #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
412 #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part */
413 #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
414 #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
415 #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
416 #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
417 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
418 #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
425 * Bank 16 - 23
431 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
432 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
433 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
434 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
435 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
436 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
437 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
438 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
439 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
440 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
441 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
442 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
443 #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
448 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
449 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
450 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
451 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
452 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
453 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
454 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
455 #define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
456 #define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
457 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
458 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
459 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
460 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
461 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
466 /* 0x0c80 - 0x0cbf: MAC 2 */
467 /* 0x0cc0 - 0x0cff: reserved */
472 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
474 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
475 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
476 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
477 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
478 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
479 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
480 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
481 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
482 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
483 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
488 /* 0x0d80 - 0x0dbf: MAC 2 */
489 /* 0x0daa - 0x0dff: reserved */
495 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */
496 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */
497 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
498 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */
500 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */
501 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
502 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
503 /* Polling Unit Registers (Yukon-2 only) */
504 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
505 #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
506 #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
507 #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. Lst Start Addr (hgh) */
508 /* ASF Subsystem Registers (Yukon-2 only) */
509 #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
510 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
511 #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
512 #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
513 #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
514 #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
515 #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
516 #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
517 #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
523 /* Status BMU Registers (Yukon-2 only) */
524 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
525 #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
526 #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status Lst Start Addr (lo) */
527 #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status Lst Strt Addr (hgh) */
528 #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Reprt Indx Reg */
529 #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Reprt Indx Reg */
530 #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Reprt Indx Reg */
531 #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Reprt Indx Reg */
532 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Indx Thrshld Reg */
533 #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
534 /* FIFO Control/Status Registers (Yukon-2 only) */
535 #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Wrt Pnter Reg */
536 #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pnter Reg */
537 #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shdw Ptr */
538 #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
539 #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shdw Level Reg */
540 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
541 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Wtrmrk Reg */
542 /* Level and ISR Timer Registers (Yukon-2 only) */
543 #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
544 #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
545 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
546 #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
547 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
548 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
549 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
550 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
551 #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
552 #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
553 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
554 #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
565 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
566 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
567 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
568 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
569 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
571 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
573 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
575 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
576 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
577 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
578 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
579 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
580 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
581 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
582 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
586 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
587 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
591 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
592 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
595 * Bank 32 - 33
600 /* offset to configuration space on Yukon-2 */
608 * Control Register Bit Definitions:
610 /* B0_CTST 24 bit Control/Status register */
611 #define Y2_VMAIN_AVAIL BIT(17) /* VMAIN available (YUKON-2 only) */
612 #define Y2_VAUX_AVAIL BIT(16) /* VAUX available (YUKON-2 only) */
613 #define Y2_HW_WOL_ON BIT(15) /* HW WOL On (Yukon-EC Ultra A1 only) */
614 #define Y2_HW_WOL_OFF BIT(14) /* HW WOL Off (Yukon-EC Ultra A1 only) */
615 #define Y2_ASF_ENABLE BIT(13) /* ASF Unit Enable (YUKON-2 only) */
616 #define Y2_ASF_DISABLE BIT(12) /* ASF Unit Disable (YUKON-2 only) */
617 #define Y2_CLK_RUN_ENA BIT(11) /* CLK_RUN Enable (YUKON-2 only) */
618 #define Y2_CLK_RUN_DIS BIT(10) /* CLK_RUN Disable (YUKON-2 only) */
619 #define Y2_LED_STAT_ON BIT(9) /* Status LED On (YUKON-2 only) */
620 #define Y2_LED_STAT_OFF BIT(8) /* Status LED Off (YUKON-2 only) */
621 #define CS_ST_SW_IRQ BIT(7) /* Set IRQ SW Request */
622 #define CS_CL_SW_IRQ BIT(6) /* Clear IRQ SW Request */
623 #define CS_STOP_DONE BIT(5) /* Stop Master is finished */
624 #define CS_STOP_MAST BIT(4) /* Command Bit to stop the master */
625 #define CS_MRST_CLR BIT(3) /* Clear Master Reset */
626 #define CS_MRST_SET BIT(2) /* Set Master Reset */
627 #define CS_RST_CLR BIT(1) /* Clear Software Reset */
628 #define CS_RST_SET BIT(0) /* Set Software Reset */
630 #define LED_STAT_ON BIT(1) /* Status LED On */
631 #define LED_STAT_OFF BIT(0) /* Status LED Off */
633 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
634 #define PC_VAUX_ENA BIT(7) /* Switch VAUX Enable */
635 #define PC_VAUX_DIS BIT(6) /* Switch VAUX Disable */
636 #define PC_VCC_ENA BIT(5) /* Switch VCC Enable */
637 #define PC_VCC_DIS BIT(4) /* Switch VCC Disable */
638 #define PC_VAUX_ON BIT(3) /* Switch VAUX On */
639 #define PC_VAUX_OFF BIT(2) /* Switch VAUX Off */
640 #define PC_VCC_ON BIT(1) /* Switch VCC On */
641 #define PC_VCC_OFF BIT(0) /* Switch VCC Off */
643 /* B0_ISRC 32 bit Interrupt Source Register */
644 /* B0_IMSK 32 bit Interrupt Mask Register */
645 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
646 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
647 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
648 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
649 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
650 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
652 #define Y2_IS_HW_ERR BIT(31) /* Interrupt HW Error */
653 #define Y2_IS_STAT_BMU BIT(30) /* Status BMU Interrupt */
654 #define Y2_IS_ASF BIT(29) /* ASF subsystem Interrupt */
655 #define Y2_IS_POLL_CHK BIT(27) /* Check IRQ from polling unit */
656 #define Y2_IS_TWSI_RDY BIT(26) /* IRQ on end of TWSI Tx */
657 #define Y2_IS_IRQ_SW BIT(25) /* SW forced IRQ */
658 #define Y2_IS_TIMINT BIT(24) /* IRQ from Timer */
659 #define Y2_IS_IRQ_PHY2 BIT(12) /* Interrupt from PHY 2 */
660 #define Y2_IS_IRQ_MAC2 BIT(11) /* Interrupt from MAC 2 */
661 #define Y2_IS_CHK_RX2 BIT(10) /* Descriptor error Rx 2 */
662 #define Y2_IS_CHK_TXS2 BIT(9) /* Descriptor error TXS 2 */
663 #define Y2_IS_CHK_TXA2 BIT(8) /* Descriptor error TXA 2 */
664 #define Y2_IS_IRQ_PHY1 BIT(4) /* Interrupt from PHY 1 */
665 #define Y2_IS_IRQ_MAC1 BIT(3) /* Interrupt from MAC 1 */
666 #define Y2_IS_CHK_RX1 BIT(2) /* Descriptor error Rx 1 */
667 #define Y2_IS_CHK_TXS1 BIT(1) /* Descriptor error TXS 1 */
668 #define Y2_IS_CHK_TXA1 BIT(0) /* Descriptor error TXA 1 */
679 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
680 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
681 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
682 #define Y2_IS_TIST_OV BIT(29) /* Time Stamp Timer overflow interrupt */
683 #define Y2_IS_SENSOR BIT(28) /* Sensor interrupt */
684 #define Y2_IS_MST_ERR BIT(27) /* Master error interrupt */
685 #define Y2_IS_IRQ_STAT BIT(26) /* Status exception interrupt */
686 #define Y2_IS_PCI_EXP BIT(25) /* PCI-Express interrupt */
687 #define Y2_IS_PCI_NEXP BIT(24) /* PCI-Express error similar to PCI error */
688 #define Y2_IS_PAR_RD2 BIT(13) /* Read RAM parity error interrupt */
689 #define Y2_IS_PAR_WR2 BIT(12) /* Write RAM parity error interrupt */
690 #define Y2_IS_PAR_MAC2 BIT(11) /* MAC hardware fault interrupt */
691 #define Y2_IS_PAR_RX2 BIT(10) /* Parity Error Rx Queue 2 */
692 #define Y2_IS_TCP_TXS2 BIT(9) /* TCP length mismatch sync Tx queue IRQ */
693 #define Y2_IS_TCP_TXA2 BIT(8) /* TCP length mismatch async Tx queue IRQ */
694 #define Y2_IS_PAR_RD1 BIT(5) /* Read RAM parity error interrupt */
695 #define Y2_IS_PAR_WR1 BIT(4) /* Write RAM parity error interrupt */
696 #define Y2_IS_PAR_MAC1 BIT(3) /* MAC hardware fault interrupt */
697 #define Y2_IS_PAR_RX1 BIT(2) /* Parity Error Rx Queue 1 */
698 #define Y2_IS_TCP_TXS1 BIT(1) /* TCP length mismatch sync Tx queue IRQ */
699 #define Y2_IS_TCP_TXA1 BIT(0) /* TCP length mismatch async Tx queue IRQ */
710 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
711 #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */
712 #define CFG_DIS_M2_CLK BIT(1) /* Disable Clock for 2nd MAC */
713 #define CFG_SNG_MAC BIT(0) /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
715 /* B2_CHIP_ID 8 bit Chip Identification Number */
718 * as they are pre-yukon 2 chips
722 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
723 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
725 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
726 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
727 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
728 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
729 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
730 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
731 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
732 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
734 /* 8 bit Chip Revision Number */
735 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
736 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
738 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
739 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
740 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
741 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
743 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
744 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
745 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
747 #define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
748 #define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
749 #define CHIP_REV_YU_EC_U_B0 3 /* Chip Rev. for Yukon-EC Ultra B0 */
750 #define CHIP_REV_YU_EC_U_B1 5 /* Chip Rev. for Yukon-EC Ultra B1 */
751 #define CHIP_REV_YU_FE_A1 1 /* Chip Rev. for Yukon-FE A1 */
752 #define CHIP_REV_YU_FE_A2 3 /* Chip Rev. for Yukon-FE A2 */
753 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-Extreme A0 */
754 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-Extreme B0 */
756 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-Supreme A0 */
757 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-Supreme B0 */
758 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-Supreme B1 */
762 /* B2_Y2_CLK_GATE - 8 bit Clock Gating (Yukon-2 only) */
763 #define Y2_STATUS_LNK2_INAC BIT(7) /* Status Link 2 inactiv (0 = activ) */
764 #define Y2_CLK_GAT_LNK2_DIS BIT(6) /* Disable clock gating Link 2 */
765 #define Y2_COR_CLK_LNK2_DIS BIT(5) /* Disable Core clock Link 2 */
766 #define Y2_PCI_CLK_LNK2_DIS BIT(4) /* Disable PCI clock Link 2 */
767 #define Y2_STATUS_LNK1_INAC BIT(3) /* Status Link 1 inactiv (0 = activ) */
768 #define Y2_CLK_GAT_LNK1_DIS BIT(2) /* Disable clock gating Link 1 */
769 #define Y2_COR_CLK_LNK1_DIS BIT(1) /* Disable Core clock Link 1 */
770 #define Y2_PCI_CLK_LNK1_DIS BIT(0) /* Disable PCI clock Link 1 */
772 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
773 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */
774 #define CFG_LINK_2_AVAIL BIT(1) /* Link 2 available */
775 #define CFG_LINK_1_AVAIL BIT(0) /* Link 1 available */
780 /* B2_E_3 8 bit lower 4 bits used for HW self test result */
783 /* B2_Y2_CLK_CTRL 32 bit Core Clck Frqncy Control Rgstr (Yukon-2/EC) */
784 /* Yukon-EC/FE */
785 #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */
786 #define Y2_CLK_DIV_VAL(x) ((x << 16) & Y2_CLK_DIV_VAL_MSK)
787 /* Yukon-2 */
788 #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */
789 #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */
791 #define Y2_CLK_SEL_VAL_2(x) ((x << 16) & Y2_CLK_SELECT2_MSK)
792 #define Y2_CLK_DIV_ENA BIT(1) /* Enable Core Clock Division */
793 #define Y2_CLK_DIV_DIS BIT(0) /* Disable Core Clock Division */
795 /* B2_TI_CTRL 8 bit Timer control */
796 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
797 #define TIM_START BIT(2) /* Start Timer */
798 #define TIM_STOP BIT(1) /* Stop Timer */
799 #define TIM_CLR_IRQ BIT(0) /* Clear Timer IRQ (!IRQM) */
801 /* B2_TI_TEST 8 Bit Timer Test */
802 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
803 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
804 #define TIM_T_ON BIT(2) /* Test mode on */
805 #define TIM_T_OFF BIT(1) /* Test mode off */
806 #define TIM_T_STEP BIT(0) /* Test step */
808 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
809 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
810 #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */
812 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
813 #define DPT_START BIT(1) /* Start Descriptor Poll Timer */
814 #define DPT_STOP BIT(0) /* Stop Descriptor Poll Timer */
816 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
817 #define TST_FRC_DPERR_MR BIT(7) /* force DATAPERR on MST RD */
818 #define TST_FRC_DPERR_MW BIT(6) /* force DATAPERR on MST WR */
819 #define TST_FRC_DPERR_TR BIT(5) /* force DATAPERR on TRG RD */
820 #define TST_FRC_DPERR_TW BIT(4) /* force DATAPERR on TRG WR */
821 #define TST_FRC_APERR_M BIT(3) /* force ADDRPERR on MST */
822 #define TST_FRC_APERR_T BIT(2) /* force ADDRPERR on TRG */
823 #define TST_CFG_WRITE_ON BIT(1) /* Enable Config Reg WR */
824 #define TST_CFG_WRITE_OFF BIT(0) /* Disable Config Reg WR */
826 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
827 #define I2C_FLAG BIT(31) /* Start read/write if WR */
828 #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
829 #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */
830 #define I2C_BURST_LEN BIT(4) /* Burst Len, 1/4 bytes */
831 #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
840 #define I2C_STOP BIT(0) /* Interrupt I2C transfer */
842 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
843 #define I2C_CLR_IRQ BIT(0) /* Clear I2C IRQ */
845 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
846 #define I2C_DATA_DIR BIT(2) /* direction of I2C_DATA */
847 #define I2C_DATA BIT(1) /* I2C Data Port */
848 #define I2C_CLK BIT(0) /* I2C Clock Port */
854 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
855 #define BSC_START BIT(1) /* Start Blink Source Counter */
856 #define BSC_STOP BIT(0) /* Stop Blink Source Counter */
858 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
859 #define BSC_SRC BIT(0) /* Blink Source, 0=Off / 1=On */
861 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
862 #define BSC_T_ON BIT(2) /* Test mode on */
863 #define BSC_T_OFF BIT(1) /* Test mode off */
864 #define BSC_T_STEP BIT(0) /* Test step */
867 #define GLB_GPIO_CLK_DEB_ENA BIT(31) /* Clock Debug Enable */
868 /* Bit(s) GLB_GPIO_RSRV_30 reserved */
871 /* Bit(s) GLB_GPIO_RSRV_25_16 reserved */
873 #define GLB_GPIO_INT_RST_D3_DIS BIT(15)
874 #define GLB_GPIO_LED_PAD_SPEED_UP BIT(14) /* LED PAD Speed Up */
875 #define GLB_GPIO_STAT_RACE_DIS BIT(13) /* Status Race Disable */
878 #define GLB_GPIO_RAND_ENA BIT(10) /* Random Enable */
879 #define GLB_GPIO_RAND_BIT_1 BIT(9) /* Random Bit 1 */
880 /* Bit(s) GLB_GPIO_RSRV_8_0 reserved */
883 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
884 #define PEX_RD_ACCESS BIT(31) /* Access Mode Read = 1, Write = 0 */
885 #define PEX_DB_ACCESS BIT(30) /* Access to debug register */
887 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
888 #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */
891 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
892 #define RI_CLR_RD_PERR BIT(9) /* Clear IRQ RAM Read Parity Err */
893 #define RI_CLR_WR_PERR BIT(8) /* Clear IRQ RAM Write Parity Err */
894 #define RI_RST_CLR BIT(1) /* Clear RAM Interface Reset */
895 #define RI_RST_SET BIT(0) /* Set RAM Interface Reset */
900 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
901 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
902 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
903 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
904 #define TXA_MAX_VAL 0x00ffffff /* Bit 23.. 0: Max TXA Timer/Cnt Val */
906 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
907 #define TXA_ENA_FSYNC BIT(7) /* Enable force of sync Tx queue */
908 #define TXA_DIS_FSYNC BIT(6) /* Disable force of sync Tx queue */
909 #define TXA_ENA_ALLOC BIT(5) /* Enable alloc of free bandwidth */
910 #define TXA_DIS_ALLOC BIT(4) /* Disable alloc of free bandwidth */
911 #define TXA_START_RC BIT(3) /* Start sync Rate Control */
912 #define TXA_STOP_RC BIT(2) /* Stop sync Rate Control */
913 #define TXA_ENA_ARB BIT(1) /* Enable Tx Arbiter */
914 #define TXA_DIS_ARB BIT(0) /* Disable Tx Arbiter */
916 /* TXA_TEST 8 bit Tx Arbiter Test Register */
917 #define TXA_INT_T_ON BIT(5) /* Tx Arb Interval Timer Test On */
918 #define TXA_INT_T_OFF BIT(4) /* Tx Arb Interval Timer Test Off */
919 #define TXA_INT_T_STEP BIT(3) /* Tx Arb Interval Timer Step */
920 #define TXA_LIM_T_ON BIT(2) /* Tx Arb Limit Timer Test On */
921 #define TXA_LIM_T_OFF BIT(1) /* Tx Arb Limit Timer Test Off */
922 #define TXA_LIM_T_STEP BIT(0) /* Tx Arb Limit Timer Step */
924 /* TXA_STAT 8 bit Tx Arbiter Status Register */
925 #define TXA_PRIO_XS BIT(0) /* sync queue has prio to send */
927 /* Q_BC 32 bit Current Byte Counter */
928 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
930 /* Rx BMU Control / Status Registers (Yukon-2) */
931 #define BMU_IDLE BIT(31) /* BMU Idle State */
932 #define BMU_RX_TCP_PKT BIT(30) /* Rx TCP Packet (when RSS Hash enab) */
933 #define BMU_RX_IP_PKT BIT(29) /* Rx IP Packet (when RSS Hash enab) */
934 #define BMU_ENA_RX_RSS_HASH BIT(15) /* Enable Rx RSS Hash */
935 #define BMU_DIS_RX_RSS_HASH BIT(14) /* Disable Rx RSS Hash */
936 #define BMU_ENA_RX_CHKSUM BIT(13) /* Enable Rx TCP/IP Checksum Check */
937 #define BMU_DIS_RX_CHKSUM BIT(12) /* Disable Rx TCP/IP Checksum Check */
938 #define BMU_CLR_IRQ_PAR BIT(11) /* Clear IRQ on Parity errors (Rx) */
939 #define BMU_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP seg. error (Tx) */
940 #define BMU_CLR_IRQ_CHK BIT(10) /* Clear IRQ Check */
941 #define BMU_STOP BIT(9) /* Stop Rx/Tx Queue */
942 #define BMU_START BIT(8) /* Start Rx/Tx Queue */
943 #define BMU_FIFO_OP_ON BIT(7) /* FIFO Operational On */
944 #define BMU_FIFO_OP_OFF BIT(6) /* FIFO Operational Off */
945 #define BMU_FIFO_ENA BIT(5) /* Enable FIFO */
946 #define BMU_FIFO_RST BIT(4) /* Reset FIFO */
947 #define BMU_OP_ON BIT(3) /* BMU Operational On */
948 #define BMU_OP_OFF BIT(2) /* BMU Operational Off */
949 #define BMU_RST_CLR BIT(1) /* Clear BMU Reset (Enable) */
950 #define BMU_RST_SET BIT(0) /* Set BMU Reset */
956 /* Tx BMU Control / Status Registers (Yukon-2) */
957 /* Bit 31: same as for Rx */
958 #define BMU_TX_IPIDINCR_ON BIT(13) /* Enable IP ID Increment */
959 #define BMU_TX_IPIDINCR_OFF BIT(12) /* Disable IP ID Increment */
960 #define BMU_TX_CLR_IRQ_TCP BIT(11) /* Clear IRQ on TCP segm. len mism. */
961 /* Bit 10..0: same as for Rx */
963 /* Q_F 32 bit Flag Register */
964 #define F_TX_CHK_AUTO_OFF BIT(31) /* Tx csum auto-calc Off (Yukon EX) */
965 #define F_TX_CHK_AUTO_ON BIT(30) /* Tx csum auto-calc On (Yukon EX) */
966 #define F_ALM_FULL BIT(27) /* Rx FIFO: almost full */
967 #define F_EMPTY BIT(27) /* Tx FIFO: empty flag */
968 #define F_FIFO_EOF BIT(26) /* Tag (EOF Flag) bit in FIFO */
969 #define F_WM_REACHED BIT(25) /* Watermark reached */
970 #define F_M_RX_RAM_DIS BIT(24) /* MAC Rx RAM Read Port disable */
971 #define F_FIFO_LEVEL (0x1f<<16) /* Bit 23..16: # of Qwords in FIFO */
972 #define F_WATER_MARK 0x0007ff /* Bit 10.. 0: Watermark */
974 /* Queue Prefetch Unt Offsts, use Y2_PREF_Q_ADDR() to addrss (Yukon-2 only) */
975 /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
976 #define PREF_UNIT_OP_ON BIT(3) /* prefetch unit operational */
977 #define PREF_UNIT_OP_OFF BIT(2) /* prefetch unit not operational */
978 #define PREF_UNIT_RST_CLR BIT(1) /* Clear Prefetch Unit Reset */
979 #define PREF_UNIT_RST_SET BIT(0) /* Set Prefetch Unit Reset */
982 /* RB_START 32 bit RAM Buffer Start Address */
983 /* RB_END 32 bit RAM Buffer End Address */
984 /* RB_WP 32 bit RAM Buffer Write Pointer */
985 /* RB_RP 32 bit RAM Buffer Read Pointer */
986 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
987 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
988 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
989 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
990 /* RB_PC 32 bit RAM Buffer Packet Counter */
991 /* RB_LEV 32 bit RAM Buffer Level Register */
992 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
994 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
995 #define RB_PC_DEC BIT(3) /* Packet Counter Decrement */
996 #define RB_PC_T_ON BIT(2) /* Packet Counter Test On */
997 #define RB_PC_T_OFF BIT(1) /* Packet Counter Test Off */
998 #define RB_PC_INC BIT(0) /* Packet Counter Increment */
1000 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
1001 #define RB_WP_T_ON BIT(6) /* Write Pointer Test On */
1002 #define RB_WP_T_OFF BIT(5) /* Write Pointer Test Off */
1003 #define RB_WP_INC BIT(4) /* Write Pointer Increment */
1004 #define RB_RP_T_ON BIT(2) /* Read Pointer Test On */
1005 #define RB_RP_T_OFF BIT(1) /* Read Pointer Test Off */
1006 #define RB_RP_INC BIT(0) /* Read Pointer Increment */
1008 /* RB_CTRL 8 bit RAM Buffer Control Register */
1009 #define RB_ENA_STFWD BIT(5) /* Enable Store & Forward */
1010 #define RB_DIS_STFWD BIT(4) /* Disable Store & Forward */
1011 #define RB_ENA_OP_MD BIT(3) /* Enable Operation Mode */
1012 #define RB_DIS_OP_MD BIT(2) /* Disable Operation Mode */
1013 #define RB_RST_CLR BIT(1) /* Clear RAM Buf STM Reset */
1014 #define RB_RST_SET BIT(0) /* Set RAM Buf STM Reset */
1019 #define RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
1021 /* Threshold values for Yukon-EC Ultra */
1058 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1059 #define WOL_CTL_LINK_CHG_OCC BIT(15)
1060 #define WOL_CTL_MAGIC_PKT_OCC BIT(14)
1061 #define WOL_CTL_PATTERN_OCC BIT(13)
1062 #define WOL_CTL_CLEAR_RESULT BIT(12)
1063 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT(11)
1064 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT(10)
1065 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT(9)
1066 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT(8)
1067 #define WOL_CTL_ENA_PME_ON_PATTERN BIT(7)
1068 #define WOL_CTL_DIS_PME_ON_PATTERN BIT(6)
1069 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT(5)
1070 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT(4)
1071 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT(3)
1072 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT(2)
1073 #define WOL_CTL_ENA_PATTERN_UNIT BIT(1)
1074 #define WOL_CTL_DIS_PATTERN_UNIT BIT(0)
1084 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1085 #define WOL_CTL_PATT_ENA(x) (BIT(0) << (x))
1087 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1088 #define WOL_PATT_FORCE_PME BIT(7) /* Generates a PME */
1093 * Marvell-PHY Registers, indirect addressed over GMAC
1095 /* Marvell-specific registers */
1096 /* 0x0b - 0x0e: reserved */
1097 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status */
1098 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control */
1099 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status */
1100 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask */
1101 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
1102 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific */
1103 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
1104 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. (Cable Diag) */
1105 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111) */
1106 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control */
1107 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override */
1108 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Spec. Ctrl 2 */
1109 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat */
1110 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic */
1111 #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Addr */
1112 #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data */
1115 #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select */
1116 #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Sel S. LED */
1117 #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N */
1118 #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N */
1119 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Ctrl Reg. 2 */
1123 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1124 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1125 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1126 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1127 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1130 /* PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg */
1131 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1132 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1133 #define PHY_M_PC_ASS_CRS_TX BIT(11) /* Assert CRS on Transmit */
1134 #define PHY_M_PC_FL_GOOD BIT(10) /* Force Link Good */
1135 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1136 #define PHY_M_PC_ENA_EXT_D BIT(7) /* Enable Ext. Distance (10BT) */
1137 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1138 #define PHY_M_PC_DIS_125CLK BIT(4) /* Disable 125 CLK */
1139 #define PHY_M_PC_MAC_POW_UP BIT(3) /* MAC Power up */
1140 #define PHY_M_PC_SQE_T_ENA BIT(2) /* SQE Test Enabled */
1141 #define PHY_M_PC_POL_R_DIS BIT(1) /* Polarity Reversal Disabled */
1142 #define PHY_M_PC_DIS_JABBER BIT(0) /* Disable Jabber */
1153 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1154 #define PHY_M_PC_DIS_LINK_P BIT(15) /* Disable Link Pulses */
1155 #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
1156 #define PHY_M_PC_DOWN_S_ENA BIT(11) /* Downshift Enable */
1158 #define PHY_M_PC_COP_TX_DIS BIT(3)
1159 #define PHY_M_PC_POW_D_ENA BIT(2)
1166 #define PHY_M_PC_ENA_DTE_DT BIT(15) /* Enable (DTE) Detect */
1167 #define PHY_M_PC_ENA_ENE_DT BIT(14) /* Enable Energy Det (sense & pulse) */
1168 #define PHY_M_PC_DIS_NLP_CK BIT(13) /* Dis. Normal Link Puls (NLP) Check */
1169 #define PHY_M_PC_ENA_LIP_NP BIT(12) /* Enable Link Partner Next Page Reg. */
1170 #define PHY_M_PC_DIS_NLP_GN BIT(11) /* Dis. Normal Link Puls Generation */
1171 #define PHY_M_PC_DIS_SCRAMB BIT(9) /* Dis. Scrambler */
1172 #define PHY_M_PC_DIS_FEFI BIT(8) /* Dis. Far End Fault Indic. (FEFI) */
1173 #define PHY_M_PC_SH_TP_SEL BIT(6) /* Shielded Twisted Pair Select */
1174 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1176 /* PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg */
1177 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1178 #define PHY_M_PS_SPEED_1000 BIT(15) /* 10 = 1000 Mbps */
1179 #define PHY_M_PS_SPEED_100 BIT(14) /* 01 = 100 Mbps */
1181 #define PHY_M_PS_FULL_DUP BIT(13) /* Full Duplex */
1182 #define PHY_M_PS_PAGE_REC BIT(12) /* Page Received */
1183 #define PHY_M_PS_SPDUP_RES BIT(11) /* Speed & Duplex Resolved */
1184 #define PHY_M_PS_LINK_UP BIT(10) /* Link Up */
1185 #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
1186 #define PHY_M_PS_MDI_X_STAT BIT(6) /* MDI Crossover Stat (1=MDIX) */
1187 #define PHY_M_PS_DOWNS_STAT BIT(5) /* Downshift Status (1=downsh.) */
1188 #define PHY_M_PS_ENDET_STAT BIT(4) /* Energy Detect Status (1=act) */
1189 #define PHY_M_PS_TX_P_EN BIT(3) /* Tx Pause Enabled */
1190 #define PHY_M_PS_RX_P_EN BIT(2) /* Rx Pause Enabled */
1191 #define PHY_M_PS_POL_REV BIT(1) /* Polarity Reversed */
1192 #define PHY_M_PS_JABBER BIT(0) /* Jabber */
1197 #define PHY_M_PS_DTE_DETECT BIT(15) /* DTE Detected */
1198 #define PHY_M_PS_RES_SPEED BIT(14) /* Resolved Speed (1=100, 0=10) */
1200 /* PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg */
1201 /* PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg */
1202 #define PHY_M_IS_AN_ERROR BIT(15) /* Auto-Negotiation Error */
1203 #define PHY_M_IS_LSP_CHANGE BIT(14) /* Link Speed Changed */
1204 #define PHY_M_IS_DUP_CHANGE BIT(13) /* Duplex Mode Changed */
1205 #define PHY_M_IS_AN_PR BIT(12) /* Page Received */
1206 #define PHY_M_IS_AN_COMPL BIT(11) /* Auto-Negotiation Completed */
1207 #define PHY_M_IS_LST_CHANGE BIT(10) /* Link Status Changed */
1208 #define PHY_M_IS_SYMB_ERROR BIT(9) /* Symbol Error */
1209 #define PHY_M_IS_FALSE_CARR BIT(8) /* False Carrier */
1210 #define PHY_M_IS_FIFO_ERROR BIT(7) /* FIFO Overflow/Underrun Error */
1211 #define PHY_M_IS_MDI_CHANGE BIT(6) /* MDI Crossover Changed */
1212 #define PHY_M_IS_DOWNSH_DET BIT(5) /* Downshift Detected */
1213 #define PHY_M_IS_END_CHANGE BIT(4) /* Energy Detect Changed */
1214 #define PHY_M_IS_DTE_CHANGE BIT(2) /* DTE Power Det. Status Changed */
1215 #define PHY_M_IS_POL_CHANGE BIT(1) /* Polarity Changed */
1216 #define PHY_M_IS_JABBER BIT(0) /* Jabber */
1223 /* PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl */
1224 #define PHY_M_EC_ENA_BC_EXT BIT(15) /* Enbl Blck Car. Ext. (88E1111 only) */
1225 #define PHY_M_EC_ENA_LIN_LB BIT(14) /* Enbl Line Loopback (88E1111 only) */
1226 #define PHY_M_EC_DIS_LINK_P BIT(12) /* Disable Link Pulses (88E1111 only) */
1227 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Mstr Downshift Cntr */
1229 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slv Downshift Cntr */
1231 #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
1233 #define PHY_M_EC_DOWN_S_ENA BIT(8) /* Downshift Enable (88E1111 only) */
1235 #define PHY_M_EC_RX_TIM_CT BIT(7) /* RGMII Rx Timing Control */
1236 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC inter speed */
1237 #define PHY_M_EC_FIB_AN_ENA BIT(3) /* Fbr Aut-Neg. Enbl (88E1011S only) */
1238 #define PHY_M_EC_DTE_D_ENA BIT(2) /* DTE Detect Enable (88E1111 only) */
1239 #define PHY_M_EC_TX_TIM_CT BIT(1) /* RGMII Tx Timing Control */
1240 #define PHY_M_EC_TRANS_DIS BIT(0) /* Transttr Disable (88E1111 only) */
1256 /* PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg */
1257 #define PHY_M_LEDC_DIS_LED BIT(15) /* Disable LED */
1258 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1259 #define PHY_M_LEDC_F_INT BIT(11) /* Force Interrupt */
1260 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1261 #define PHY_M_LEDC_DP_C_LSB BIT(7) /* Duplex Control (LSB, 88E1111 only) */
1262 #define PHY_M_LEDC_TX_C_LSB BIT(6) /* Tx Control (LSB, 88E1111 only) */
1263 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
1265 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1267 #define PHY_M_LEDC_DP_CTRL BIT(2) /* Duplex Control */
1268 #define PHY_M_LEDC_DP_C_MSB BIT(2) /* Duplex Control (MSB, 88E1111 only) */
1269 #define PHY_M_LEDC_RX_CTRL BIT(1) /* Rx Activity / Link */
1270 #define PHY_M_LEDC_TX_CTRL BIT(0) /* Tx Activity / Link */
1271 #define PHY_M_LEDC_TX_C_MSB BIT(0) /* Tx Control (MSB, 88E1111 only) */
1292 /* PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg */
1293 #define PHY_M_LED_MO_SGMII(x) (x << 14) /* Bit 15..14: SGMII AN Tmr */
1294 #define PHY_M_LED_MO_DUP(x) (x << 10) /* Bit 11..10: Duplex */
1295 #define PHY_M_LED_MO_10(x) (x << 8) /* Bit 9.. 8: Link 10 */
1296 #define PHY_M_LED_MO_100(x) (x << 6) /* Bit 7.. 6: Link 100 */
1297 #define PHY_M_LED_MO_1000(x) (x << 4) /* Bit 5.. 4: Link 1000 */
1298 #define PHY_M_LED_MO_RX(x) (x << 2) /* Bit 3.. 2: Rx */
1299 #define PHY_M_LED_MO_TX(x) (x) /* Bit 1.. 0: Tx */
1306 /* PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 */
1307 #define PHY_M_EC2_FI_IMPED BIT(6) /* Fiber Input Impedance */
1308 #define PHY_M_EC2_FO_IMPED BIT(5) /* Fiber Output Impedance */
1309 #define PHY_M_EC2_FO_M_CLK BIT(4) /* Fiber Mode Clock Enable */
1310 #define PHY_M_EC2_FO_BOOST BIT(3) /* Fiber Output Boost */
1311 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Otpt Amplitude */
1313 /* PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status */
1314 #define PHY_M_FC_AUTO_SEL BIT(15) /* Fiber/Copper Auto Sel. Dis. */
1315 #define PHY_M_FC_AN_REG_ACC BIT(14) /* Fiber/Copper AN Reg. Access */
1316 #define PHY_M_FC_RESOLUTION BIT(13) /* Fiber/Copper Resolution */
1317 #define PHY_M_SER_IF_AN_BP BIT(12) /* Ser. IF AN Bypass Enable */
1318 #define PHY_M_SER_IF_BP_ST BIT(11) /* Ser. IF AN Bypass Status */
1319 #define PHY_M_IRQ_POLARITY BIT(10) /* IRQ polarity */
1320 #define PHY_M_DIS_AUT_MED BIT(9) /* Disable Aut. Medium Reg. Selection */
1322 #define PHY_M_UNDOC1 BIT(7) /* undocumented bit !! */
1323 #define PHY_M_DTE_POW_STAT BIT(4) /* DTE Power Status (88E1111 only) */
1324 #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: cpy HWCFG MODE[3:0] */
1326 /* PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg */
1327 #define PHY_M_CABD_ENA_TEST BIT(15) /* Enable Test (Page 0) */
1328 #define PHY_M_CABD_DIS_WAIT BIT(15) /* Disable Waiting Period (Page 1) */
1330 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
1331 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
1333 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
1342 /* PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. */
1343 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8:LED2 Msk (LNK) */
1368 /* PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 */
1369 #define PHY_M_FESC_DIS_WAIT BIT(2) /* Disable TDR Waiting Period */
1370 #define PHY_M_FESC_ENA_MCLK BIT(1) /* Enable MAC Rx Clock in sleep mode */
1371 #define PHY_M_FESC_SEL_CL_A BIT(0) /* Select Class A driver (100B-TX) */
1373 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1374 /* PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl */
1375 #define PHY_M_FIB_FORCE_LNK BIT(10) /* Force Link Good */
1376 #define PHY_M_FIB_SIGD_POL BIT(9) /* SIGDET Polarity */
1377 #define PHY_M_FIB_TX_DIS BIT(3) /* Transmitter Disable */
1379 /* PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl */
1380 #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
1381 #define PHY_M_MAC_GMIF_PUP BIT(3)
1382 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1384 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1387 /* PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. */
1388 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1389 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1390 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Msk */
1391 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1398 /* PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. */
1399 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Msk */
1400 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Msk */
1401 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Msk */
1402 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Msk */
1403 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Msk */
1404 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Msk */
1416 * The GMAC registers are 16 or 32 bits wide.
1417 * The GMACs host processor interface is 16 bits wide,
1418 * therefore ALL registers will be addressed with 16 bit accesses.
1424 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1425 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1426 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1427 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1428 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1429 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1430 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1433 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1434 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1435 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1436 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1437 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1438 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1441 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1442 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1443 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1444 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1447 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1448 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1449 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1452 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1453 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1454 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1457 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1458 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1459 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1466 * MIB Counters base address definitions (low word) -
1467 * use offset 4 for access to high word (32 bit r/o)
1471 #define GM_RXF_MPAUSE (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Rx'd */
1482 #define GM_RXF_127B (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1483 #define GM_RXF_255B (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1484 #define GM_RXF_511B (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1485 #define GM_RXF_1023B (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1486 #define GM_RXF_1518B (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1487 #define GM_RXF_MAX_SZ (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1500 #define GM_TXF_127B (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1501 #define GM_TXF_255B (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1502 #define GM_TXF_511B (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1503 #define GM_TXF_1023B (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1504 #define GM_TXF_1518B (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1505 #define GM_TXF_MAX_SZ (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1515 * GMAC Bit Definitions
1517 * If the bit access behaviour differs from the register access behaviour
1518 * (r/w, r/o) this is documented after the bit number.
1519 * The following bit access behaviours are used:
1524 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1525 #define GM_GPSR_SPEED BIT(15) /* Port Speed (1 = 100 Mbps) */
1526 #define GM_GPSR_DUPLEX BIT(14) /* Duplex Mode (1 = Full) */
1527 #define GM_GPSR_FC_TX_DIS BIT(13) /* Tx Flow-Control Mode Disabled */
1528 #define GM_GPSR_LINK_UP BIT(12) /* Link Up Status */
1529 #define GM_GPSR_PAUSE BIT(11) /* Pause State */
1530 #define GM_GPSR_TX_ACTIVE BIT(10) /* Tx in Progress */
1531 #define GM_GPSR_EXC_COL BIT(9) /* Excessive Collisions Occured */
1532 #define GM_GPSR_LAT_COL BIT(8) /* Late Collisions Occured */
1533 #define GM_GPSR_PHY_ST_CH BIT(5) /* PHY Status Change */
1534 #define GM_GPSR_GIG_SPEED BIT(4) /* Gigabit Speed (1 = 1000 Mbps) */
1535 #define GM_GPSR_PART_MODE BIT(3) /* Partition mode */
1536 #define GM_GPSR_FC_RX_DIS BIT(2) /* Rx Flow-Control Mode Disabled */
1538 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1539 #define GM_GPCR_RMII_PH_ENA BIT(15) /* Enbl RMII for PHY (Yukon-FE only) */
1540 #define GM_GPCR_RMII_LB_ENA BIT(14) /* Enable RMII Lpbck (Yukon-FE only) */
1541 #define GM_GPCR_FC_TX_DIS BIT(13) /* Disable Tx Flow-Control Mode */
1542 #define GM_GPCR_TX_ENA BIT(12) /* Enable Transmit */
1543 #define GM_GPCR_RX_ENA BIT(11) /* Enable Receive */
1544 #define GM_GPCR_LOOP_ENA BIT(9) /* Enable MAC Loopback Mode */
1545 #define GM_GPCR_PART_ENA BIT(8) /* Enable Partition Mode */
1546 #define GM_GPCR_GIGS_ENA BIT(7) /* Gigabit Speed (1000 Mbps) */
1547 #define GM_GPCR_FL_PASS BIT(6) /* Force Link Pass */
1548 #define GM_GPCR_DUP_FULL BIT(5) /* Full Duplex Mode */
1549 #define GM_GPCR_FC_RX_DIS BIT(4) /* Disable Rx Flow-Control Mode */
1550 #define GM_GPCR_SPEED_100 BIT(3) /* Port Speed 100 Mbps */
1551 #define GM_GPCR_AU_DUP_DIS BIT(2) /* Disable Auto-Update Duplex */
1552 #define GM_GPCR_AU_FCT_DIS BIT(1) /* Disable Auto-Update Flow-C. */
1553 #define GM_GPCR_AU_SPD_DIS BIT(0) /* Disable Auto-Update Speed */
1559 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1560 #define GM_TXCR_FORCE_JAM BIT(15) /* Force Jam / Flow-Control */
1561 #define GM_TXCR_CRC_DIS BIT(14) /* Disable insertion of CRC */
1562 #define GM_TXCR_PAD_DIS BIT(13) /* Disable padding of packets */
1563 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collisn Threshld Msk */
1564 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
1565 /* (Yukon-2 only) */
1570 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1571 #define GM_RXCR_UCF_ENA BIT(15) /* Enable Unicast filtering */
1572 #define GM_RXCR_MCF_ENA BIT(14) /* Enable Multicast filtering */
1573 #define GM_RXCR_CRC_DIS BIT(13) /* Remove 4-byte CRC */
1574 #define GM_RXCR_PASS_FC BIT(12) /* Pass FC pckts FIFO (Yukon-1 only) */
1576 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1577 #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Lngth Msk */
1578 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
1579 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam Data Msk */
1580 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
1581 /* (Yukon-2 only) */
1593 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1594 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
1595 /* r/o on Yukon, r/w on Yukon-EC */
1596 #define GM_SMOD_LIMIT_4 BIT(10) /* 4 consecutive Tx trials */
1597 #define GM_SMOD_VLAN_ENA BIT(9) /* Enable VLAN (Max. Frame Len) */
1598 #define GM_SMOD_JUMBO_ENA BIT(8) /* Enable Jumbo (Max. Frame Len) */
1599 #define GM_NEW_FLOW_CTRL BIT(6) /* Enable New Flow-Control */
1600 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Intr-Pckt Gap (IPG) */
1608 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1609 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Addr */
1610 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Addr */
1611 #define GM_SMI_CT_OP_RD BIT(5) /* OpCode Read (0=Write) */
1612 #define GM_SMI_CT_RD_VAL BIT(4) /* Read Valid (Read completed) */
1613 #define GM_SMI_CT_BUSY BIT(3) /* Busy (Operation in progress) */
1618 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1619 #define GM_PAR_MIB_CLR BIT(5) /* Set MIB Clear Counter Mode */
1620 #define GM_PAR_MIB_TST BIT(4) /* MIB Load Counter (Test Mode) */
1623 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1624 #define GMR_FS_VLAN BIT(13) /* VLAN Packet */
1625 #define GMR_FS_JABBER BIT(12) /* Jabber Packet */
1626 #define GMR_FS_UN_SIZE BIT(11) /* Undersize Packet */
1627 #define GMR_FS_MC BIT(10) /* Multicast Packet */
1628 #define GMR_FS_BC BIT(9) /* Broadcast Packet */
1629 #define GMR_FS_RX_OK BIT(8) /* Receive OK (Good Packet) */
1630 #define GMR_FS_GOOD_FC BIT(7) /* Good Flow-Control Packet */
1631 #define GMR_FS_BAD_FC BIT(6) /* Bad Flow-Control Packet */
1632 #define GMR_FS_MII_ERR BIT(5) /* MII Error */
1633 #define GMR_FS_LONG_ERR BIT(4) /* Too Long Packet */
1634 #define GMR_FS_FRAGMENT BIT(3) /* Fragment */
1635 #define GMR_FS_CRC_ERR BIT(1) /* CRC Error */
1636 #define GMR_FS_RX_FF_OV BIT(0) /* Rx FIFO Overflow */
1638 #define GMR_FS_LEN_SHIFT 16
1656 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1657 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1658 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1659 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1660 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1661 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1662 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1663 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh. */
1664 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1665 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1666 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1667 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1668 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1669 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1671 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1672 #define RX_TRUNC_ON BIT(27) /* enable packet truncation */
1673 #define RX_TRUNC_OFF BIT(26) /* disable packet truncation */
1674 #define RX_VLAN_STRIP_ON BIT(25) /* enable VLAN stripping */
1675 #define RX_VLAN_STRIP_OFF BIT(24) /* disable VLAN stripping */
1676 #define GMF_RX_OVER_ON BIT(19) /* flushing on receive overrun */
1677 #define GMF_RX_OVER_OFF BIT(18) /* flushing on receive overrun */
1678 #define GMF_WP_TST_ON BIT(14) /* Write Pointer Test On */
1679 #define GMF_WP_TST_OFF BIT(13) /* Write Pointer Test Off */
1680 #define GMF_WP_STEP BIT(12) /* Write Pointer Step/Increment */
1681 #define GMF_RP_TST_ON BIT(10) /* Read Pointer Test On */
1682 #define GMF_RP_TST_OFF BIT(9) /* Read Pointer Test Off */
1683 #define GMF_RP_STEP BIT(8) /* Read Pointer Step/Increment */
1684 #define GMF_RX_F_FL_ON BIT(7) /* Rx FIFO Flush Mode On */
1685 #define GMF_RX_F_FL_OFF BIT(6) /* Rx FIFO Flush Mode Off */
1686 #define GMF_CLI_RX_FO BIT(5) /* Clear IRQ Rx FIFO Overrun */
1687 #define GMF_CLI_RX_FC BIT(4) /* Clear IRQ Rx Frame Complete */
1688 #define GMF_OPER_ON BIT(3) /* Operational Mode On */
1689 #define GMF_OPER_OFF BIT(2) /* Operational Mode Off */
1690 #define GMF_RST_CLR BIT(1) /* Clear GMAC FIFO Reset */
1691 #define GMF_RST_SET BIT(0) /* Set GMAC FIFO Reset */
1693 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1694 #define TX_STFW_DIS BIT(31) /* Disable Store & Forward (Yukon-EC Ultra) */
1695 #define TX_STFW_ENA BIT(30) /* Enable Store & Forward (Yukon-EC Ultra) */
1696 #define TX_VLAN_TAG_ON BIT(25) /* enable VLAN tagging */
1697 #define TX_VLAN_TAG_OFF BIT(24) /* disable VLAN tagging */
1698 #define TX_JUMBO_ENA BIT(23) /* Enable Jumbo Mode (Yukon-EC Ultra) */
1699 #define TX_JUMBO_DIS BIT(22) /* Disable Jumbo Mode (Yukon-EC Ultra) */
1700 #define GMF_WSP_TST_ON BIT(18) /* Write Shadow Pointer Test On */
1701 #define GMF_WSP_TST_OFF BIT(17) /* Write Shadow Pointer Test Off */
1702 #define GMF_WSP_STEP BIT(16) /* Write Shadow Pointer Step/Increment */
1704 #define GMF_CLI_TX_FU BIT(6) /* Clear IRQ Tx FIFO Underrun */
1705 #define GMF_CLI_TX_FC BIT(5) /* Clear IRQ Tx Frame Complete */
1706 #define GMF_CLI_TX_PE BIT(4) /* Clear IRQ Tx Parity Error */
1715 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1716 #define GMT_ST_START BIT(2) /* Start Time Stamp Timer */
1717 #define GMT_ST_STOP BIT(1) /* Stop Time Stamp Timer */
1718 #define GMT_ST_CLR_IRQ BIT(0) /* Clear Time Stamp Timer IRQ */
1720 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
1721 #define PC_CLR_IRQ_CHK BIT(5) /* Clear IRQ Check */
1722 #define PC_POLL_RQ BIT(4) /* Poll Request Start */
1723 #define PC_POLL_OP_ON BIT(3) /* Operational Mode On */
1724 #define PC_POLL_OP_OFF BIT(2) /* Operational Mode Off */
1725 #define PC_POLL_RST_CLR BIT(1) /* Clear Polling Unit Reset (Enable) */
1726 #define PC_POLL_RST_SET BIT(0) /* Set Polling Unit Reset */
1728 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1730 #define Y2_ASF_AHB_RST BIT(9) /* AHB bridge reset */
1731 #define Y2_ASF_CPU_MODE BIT(8) /* ASF CPU reset mode */
1732 #define Y2_ASF_OS_PRES BIT(4) /* ASF operation system present */
1733 #define Y2_ASF_RESET BIT(3) /* ASF system in reset state */
1734 #define Y2_ASF_RUNNING BIT(2) /* ASF system operational */
1735 #define Y2_ASF_CLR_HSTI BIT(1) /* Clear ASF IRQ */
1736 #define Y2_ASF_IRQ BIT(0) /* Issue an IRQ to ASF system */
1742 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1744 #define Y2_ASF_CLR_ASFI BIT(1) /* Clear host IRQ */
1745 #define Y2_ASF_HOST_IRQ BIT(0) /* Issue an IRQ to HOST system */
1747 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1748 #define SC_STAT_CLR_IRQ BIT(4) /* Status Burst IRQ clear */
1749 #define SC_STAT_OP_ON BIT(3) /* Operational Mode On */
1750 #define SC_STAT_OP_OFF BIT(2) /* Operational Mode Off */
1751 #define SC_STAT_RST_CLR BIT(1) /* Clear Status Unit Reset (Enable) */
1752 #define SC_STAT_RST_SET BIT(0) /* Set Status Unit Reset */
1754 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1755 #define GMC_SET_RST BIT(15) /* MAC SEC RST */
1756 #define GMC_SEC_RST_OFF BIT(14) /* MAC SEC RST OFF */
1757 #define GMC_BYP_MACSECRX_ON BIT(13) /* Bypass macsec RX */
1758 #define GMC_BYP_MACSECRX_OFF BIT(12) /* Bypass macsec RX off */
1759 #define GMC_BYP_MACSECTX_ON BIT(11) /* Bypass macsec TX */
1760 #define GMC_BYP_MACSECTX_OFF BIT(10) /* Bypass macsec TX off */
1761 #define GMC_BYP_RETR_ON BIT(9) /* Bypass retransmit FIFO On */
1762 #define GMC_BYP_RETR_OFF BIT(8) /* Bypass retransmit FIFO Off */
1763 #define GMC_H_BURST_ON BIT(7) /* Half Duplex Burst Mode On */
1764 #define GMC_H_BURST_OFF BIT(6) /* Half Duplex Burst Mode Off */
1765 #define GMC_F_LOOPB_ON BIT(5) /* FIFO Loopback On */
1766 #define GMC_F_LOOPB_OFF BIT(4) /* FIFO Loopback Off */
1767 #define GMC_PAUSE_ON BIT(3) /* Pause On */
1768 #define GMC_PAUSE_OFF BIT(2) /* Pause Off */
1769 #define GMC_RST_CLR BIT(1) /* Clear GMAC Reset */
1770 #define GMC_RST_SET BIT(0) /* Set GMAC Reset */
1772 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1773 #define GPC_SEL_BDT BIT(28) /* Select Bi-Dir. Transfer for MDC/MDIO */
1774 #define GPC_INT_POL BIT(27) /* IRQ Polarity is Active Low */
1775 #define GPC_75_OHM BIT(26) /* Use 75 Ohm Termination instead of 50 */
1776 #define GPC_DIS_FC BIT(25) /* Disable Automatic Fiber/Copper Detection */
1777 #define GPC_DIS_SLEEP BIT(24) /* Disable Energy Detect */
1778 #define GPC_HWCFG_M_3 BIT(23) /* HWCFG_MODE[3] */
1779 #define GPC_HWCFG_M_2 BIT(22) /* HWCFG_MODE[2] */
1780 #define GPC_HWCFG_M_1 BIT(21) /* HWCFG_MODE[1] */
1781 #define GPC_HWCFG_M_0 BIT(20) /* HWCFG_MODE[0] */
1782 #define GPC_ANEG_0 BIT(19) /* ANEG[0] */
1783 #define GPC_ENA_XC BIT(18) /* Enable MDI crossover */
1784 #define GPC_DIS_125 BIT(17) /* Disable 125 MHz clock */
1785 #define GPC_ANEG_3 BIT(16) /* ANEG[3] */
1786 #define GPC_ANEG_2 BIT(15) /* ANEG[2] */
1787 #define GPC_ANEG_1 BIT(14) /* ANEG[1] */
1788 #define GPC_ENA_PAUSE BIT(13) /* Enable Pause (SYM_OR_REM) */
1789 #define GPC_PHYADDR_4 BIT(12) /* Bit 4 of Phy Addr */
1790 #define GPC_PHYADDR_3 BIT(11) /* Bit 3 of Phy Addr */
1791 #define GPC_PHYADDR_2 BIT(10) /* Bit 2 of Phy Addr */
1792 #define GPC_PHYADDR_1 BIT(9) /* Bit 1 of Phy Addr */
1793 #define GPC_PHYADDR_0 BIT(8) /* Bit 0 of Phy Addr */
1794 #define GPC_RST_CLR BIT(1) /* Clear GPHY Reset */
1795 #define GPC_RST_SET BIT(0) /* Set GPHY Reset */
1797 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1798 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1799 #define GM_IS_RX_CO_OV BIT(5) /* Receive Counter Overflow IRQ */
1800 #define GM_IS_TX_CO_OV BIT(4) /* Transmit Counter Overflow IRQ */
1801 #define GM_IS_TX_FF_UR BIT(3) /* Transmit FIFO Underrun */
1802 #define GM_IS_TX_COMPL BIT(2) /* Frame Transmission Complete */
1803 #define GM_IS_RX_FF_OR BIT(1) /* Receive FIFO Overrun */
1804 #define GM_IS_RX_COMPL BIT(0) /* Frame Reception Complete */
1808 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1809 #define GMLC_RST_CLR BIT(1) /* Clear GMAC Link Reset */
1810 #define GMLC_RST_SET BIT(0) /* Set GMAC Link Reset */
1817 ddi_put32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)), (v))
1819 ddi_put16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)), (v))
1821 ddi_put8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)), (v))
1824 ddi_get32(d->d_regsh, (uint32_t *)(void *)(d->d_regs + (reg)))
1826 ddi_get16(d->d_regsh, (uint16_t *)(void *)(d->d_regs + (reg)))
1828 ddi_get8(d->d_regsh, (uint8_t *)(void *)(d->d_regs + (reg)))
1839 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
1852 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status))
1855 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status))
1858 (ddi_get32((ring)->r_acch, &(ring)->r_kaddr[i].desc_control))
1861 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status, v))
1864 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_status, v))
1867 (ddi_put32((ring)->r_acch, &(ring)->r_kaddr[i].desc_control, v))
1870 (void) ddi_dma_sync((ring)->r_dmah, (i) * sizeof (yge_desc_t), \
1874 bzero((ring)->r_kaddr, (ring)->r_size)
1877 (void) ddi_dma_sync((ring)->r_dmah, 0, 0, (flags))
1880 (void) ddi_dma_sync(b->b_dmah, 0, 0, flags)
1942 /* YUKON-2 bit values */
1948 /* YUKON-2 Control flags */
1965 /* YUKON-2 Rx/Tx opcodes defines */
1984 /* YUKON-2 STATUS opcodes defines */
1994 /* YUKON-2 SPECIAL opcodes defines */
2000 /* Descriptor Bit Definition */
2003 #define BMU_OWN BIT(31) /* OWN bit: 0=host/1=BMU */
2004 #define BMU_STF BIT(30) /* Start of Frame */
2005 #define BMU_EOF BIT(29) /* End of Frame */
2006 #define BMU_IRQ_EOB BIT(28) /* Req "End of Buffer" IRQ */
2007 #define BMU_IRQ_EOF BIT(27) /* Req "End of Frame" IRQ */
2009 #define BMU_STFWD BIT(26) /* (Tx) Store & Forward Frame */
2010 #define BMU_NO_FCS BIT(25) /* (Tx) Disable MAC FCS (CRC) generation */
2011 #define BMU_SW BIT(24) /* (Tx) 1 bit res. for SW use */
2013 #define BMU_DEV_0 BIT(26) /* (Rx) Transfer data to Dev0 */
2014 #define BMU_STAT_VAL BIT(25) /* (Rx) Rx Status Valid */
2015 #define BMU_TIST_VAL BIT(24) /* (Rx) Rx TimeStamp Valid */
2016 /* Bit 23..16: BMU Check Opcodes */
2017 #define BMU_CHECK (0x55<<16) /* Default BMU check */
2018 #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */
2019 #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */
2020 #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */
2056 /* Note: We could conceivably change this to support 64-bit */
2068 #define YGE_PROC_MAX (YGE_RX_RING_CNT - 1)
2198 * All of these locks are shaerd between both ports on a multi-port device.
2207 #define RX_LOCK(dev) mutex_enter(&dev->d_rxlock);
2208 #define RX_UNLOCK(dev) mutex_exit(&dev->d_rxlock);
2209 #define TX_LOCK(dev) mutex_enter(&dev->d_txlock);
2210 #define TX_UNLOCK(dev) mutex_exit(&dev->d_txlock);
2211 #define PHY_LOCK(dev) mutex_enter(&dev->d_phylock);
2212 #define PHY_UNLOCK(dev) mutex_exit(&dev->d_phylock);
2224 #define TASK_LOCK(dev) mutex_enter(&(dev)->d_task_mtx)
2225 #define TASK_UNLOCK(dev) mutex_exit(&(dev)->d_task_mtx)
2226 #define TASK_WAIT(dev) cv_wait(&(dev)->d_task_cv, &(dev)->d_task_mtx)
2227 #define TASK_SIGNAL(dev) cv_signal(&(dev)->d_task_cv)
2229 #define YGE_USECS(sc, us) ((sc)->d_clock * (us))
2286 (((dev)->d_Features[((ReqFeature) & 0x30000000UL) >> 28] &\
2295 #define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */
2303 #define HWF_NEW_FLOW_CONTROL 0x00040000UL /* New Flow-Control support */
2313 #define HWF_WA_DEV_4217 0x10400000UL /* 4.217 (PCI-E blockage) */
2335 #define HWF_WA_DEV_428 0x10000004UL /* 4.28 (Poll-U &BigEndi) */
2337 /* for Yu-L Rev. A0 only */