368 		CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),  in yge_mii_notify()
424 		CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);  in yge_mii_notify()
644 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),  in yge_phy_power()
646 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),  in yge_phy_power()
757 		CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);  in yge_reset()
758 		CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);  in yge_reset()
760 		CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);  in yge_reset()
761 		CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);  in yge_reset()
764 			CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL),  in yge_reset()
768 		CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);  in yge_reset()
795 		CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);  in yge_reset()
2027 	status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));  in yge_intr_gmac()
2031 		CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO);  in yge_intr_gmac()
2037 		CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU);  in yge_intr_gmac()
2072 		CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),  in yge_handle_hwerr()
2387 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),  in yge_set_tx_stfwd()
2390 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),  in yge_set_tx_stfwd()
2397 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR),  in yge_set_tx_stfwd()
2400 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),  in yge_set_tx_stfwd()
2404 			CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),  in yge_set_tx_stfwd()
2438 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET);  in yge_start_port()
2439 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR);  in yge_start_port()
2440 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF);  in yge_start_port()
2442 		CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL),  in yge_start_port()
2452 	(void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));  in yge_start_port()
2484 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);  in yge_start_port()
2485 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR);  in yge_start_port()
2490 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);  in yge_start_port()
2496 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);  in yge_start_port()
2508 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);  in yge_start_port()
2511 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);  in yge_start_port()
2512 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR);  in yge_start_port()
2513 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON);  in yge_start_port()
2516 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);  in yge_start_port()
2517 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);  in yge_start_port()
2523 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),  in yge_start_port()
2525 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),  in yge_start_port()
2528 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),  in yge_start_port()
2530 			CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),  in yge_start_port()
2540 		reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));  in yge_start_port()
2542 		CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);  in yge_start_port()
2549 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL),  in yge_start_port()
2552 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB);  in yge_start_port()
2762 	CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0);  in yge_stop_port()
2765 	CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB);  in yge_stop_port()
2778 	CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);  in yge_stop_port()
2780 	CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF);  in yge_stop_port()
2812 	CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);  in yge_stop_port()