382 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)  in ural_write()  function
934 	ural_write(sc, RAL_PHY_CSR7, tmp);  in ural_bbp_write()
944 	ural_write(sc, RAL_PHY_CSR7, val);  in ural_bbp_read()
975 	ural_write(sc, RAL_PHY_CSR9,  tmp & 0xffff);  in ural_rf_write()
976 	ural_write(sc, RAL_PHY_CSR10, tmp >> 16);  in ural_rf_write()
1119 	ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_enable_tsf_sync()
1122 	ural_write(sc, RAL_TXRX_CSR18, tmp);  in ural_enable_tsf_sync()
1127 	ural_write(sc, RAL_TXRX_CSR20, tmp);  in ural_enable_tsf_sync()
1135 	ural_write(sc, RAL_TXRX_CSR19, tmp);  in ural_enable_tsf_sync()
1166 	ural_write(sc, RAL_MAC_CSR10, slottime);  in ural_update_slot()
1167 	ural_write(sc, RAL_MAC_CSR11, sifs);  in ural_update_slot()
1168 	ural_write(sc, RAL_MAC_CSR12, eifs);  in ural_update_slot()
1182 	ural_write(sc, RAL_TXRX_CSR10, tmp);  in ural_set_txpreamble()
1193 		ural_write(sc, RAL_TXRX_CSR11, 0x3);  in ural_set_basicrates()
1196 		ural_write(sc, RAL_TXRX_CSR11, 0x150);  in ural_set_basicrates()
1199 		ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_set_basicrates()
1209 	ural_write(sc, RAL_MAC_CSR5, tmp);  in ural_set_bssid()
1212 	ural_write(sc, RAL_MAC_CSR6, tmp);  in ural_set_bssid()
1215 	ural_write(sc, RAL_MAC_CSR7, tmp);  in ural_set_bssid()
1226 	ural_write(sc, RAL_MAC_CSR2, tmp);  in ural_set_macaddr()
1229 	ural_write(sc, RAL_MAC_CSR3, tmp);  in ural_set_macaddr()
1232 	ural_write(sc, RAL_MAC_CSR4, tmp);  in ural_set_macaddr()
1249 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_update_promisc()
1341 	ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7));  in ural_set_txantenna()
1344 	ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7));  in ural_set_txantenna()
1407 			ural_write(sc, RAL_TXRX_CSR19, 0);  in ural_newstate()
1409 			ural_write(sc, RAL_MAC_CSR20, 0);  in ural_newstate()
1441 		ural_write(sc, RAL_MAC_CSR20, 1);  in ural_newstate()
1655 	ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX);  in ural_stop()
1658 	ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP);  in ural_stop()
1659 	ural_write(sc, RAL_MAC_CSR1, 0);  in ural_stop()
1674 	ural_write(sc, 0x308, 0x00f0);	/* magic */  in ural_init()
1680 		ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);  in ural_init()
1697 	ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY);  in ural_init()
1700 	ural_write(sc, RAL_TXRX_CSR11, 0x15f);  in ural_init()
1736 	ural_write(sc, RAL_TXRX_CSR2, tmp);  in ural_init()