Lines Matching full:rx
18 #define RCR 0x05U /* rx control register */
19 #define RSR 0x06U /* rx status register */
20 #define ROCR 0x07U /* rx overflow counter register */
71 #define NSR_RXOV 0x02U /* rx fifo overflow */
72 #define NSR_RXRDY 0x01U /* rx packet ready */
119 /* rx control register */
126 #define RCR_RXEN 0x01U /* rx enable */
138 /* rx status register */
192 #define FCTR_HWOT 0xf0U /* rx fifo high water overflow threshold */
195 #define FCTR_LWOT 0x0fU /* rx fifo low water overflow threshold */
199 /* rx/tx flow control register */
205 #define FCR_BKPS 0x04U /* rx pause packet current status (r/c) */
206 #define FCR_RXPCS 0x02U /* rx pause packet current status (ro) */
250 #define WCR_SAMPLEST 0x02U /* sample frame rx occur ro */
251 #define WCR_MAGICST 0x01U /* magic pkt rx occur ro */
305 #define TUSR_RXFAULT 0x80U /* indicate rx has unexpected condition */