Lines Matching refs:rgep
28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) argument
29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) argument
30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) argument
31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) argument
52 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno);
56 rge_reg_get32(rge_t *rgep, uintptr_t regno) in rge_reg_get32() argument
59 (void *)rgep, regno)); in rge_reg_get32()
61 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); in rge_reg_get32()
64 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data);
68 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) in rge_reg_put32() argument
71 (void *)rgep, regno, data)); in rge_reg_put32()
73 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); in rge_reg_put32()
76 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits);
80 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) in rge_reg_set32() argument
85 (void *)rgep, regno, bits)); in rge_reg_set32()
87 regval = rge_reg_get32(rgep, regno); in rge_reg_set32()
89 rge_reg_put32(rgep, regno, regval); in rge_reg_set32()
92 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits);
96 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) in rge_reg_clr32() argument
101 (void *)rgep, regno, bits)); in rge_reg_clr32()
103 regval = rge_reg_get32(rgep, regno); in rge_reg_clr32()
105 rge_reg_put32(rgep, regno, regval); in rge_reg_clr32()
108 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno);
112 rge_reg_get16(rge_t *rgep, uintptr_t regno) in rge_reg_get16() argument
115 (void *)rgep, regno)); in rge_reg_get16()
117 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); in rge_reg_get16()
120 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data);
124 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) in rge_reg_put16() argument
127 (void *)rgep, regno, data)); in rge_reg_put16()
129 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); in rge_reg_put16()
132 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno);
136 rge_reg_get8(rge_t *rgep, uintptr_t regno) in rge_reg_get8() argument
139 (void *)rgep, regno)); in rge_reg_get8()
141 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); in rge_reg_get8()
144 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data);
148 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) in rge_reg_put8() argument
151 (void *)rgep, regno, data)); in rge_reg_put8()
153 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); in rge_reg_put8()
156 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits);
160 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) in rge_reg_set8() argument
165 (void *)rgep, regno, bits)); in rge_reg_set8()
167 regval = rge_reg_get8(rgep, regno); in rge_reg_set8()
169 rge_reg_put8(rgep, regno, regval); in rge_reg_set8()
172 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits);
176 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) in rge_reg_clr8() argument
181 (void *)rgep, regno, bits)); in rge_reg_clr8()
183 regval = rge_reg_get8(rgep, regno); in rge_reg_clr8()
185 rge_reg_put8(rgep, regno, regval); in rge_reg_clr8()
188 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii);
192 rge_mii_get16(rge_t *rgep, uintptr_t mii) in rge_mii_get16() argument
199 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); in rge_mii_get16()
206 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); in rge_mii_get16()
211 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); in rge_mii_get16()
215 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
219 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) in rge_mii_put16() argument
228 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); in rge_mii_put16()
235 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); in rge_mii_put16()
239 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", in rge_mii_put16()
243 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data);
247 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) in rge_ephy_put16() argument
256 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); in rge_ephy_put16()
263 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); in rge_ephy_put16()
267 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", in rge_ephy_put16()
299 rge_phydump(rge_t *rgep) in rge_phydump() argument
304 ASSERT(mutex_owned(rgep->genlock)); in rge_phydump()
307 regs[i] = rge_mii_get16(rgep, i); in rge_phydump()
320 rge_phy_check(rge_t *rgep) in rge_phy_check() argument
324 if (rgep->param_link_up == LINK_STATE_DOWN) { in rge_phy_check()
329 if (rgep->chipid.phy_ver == PHY_VER_S) { in rge_phy_check()
330 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); in rge_phy_check()
332 rgep->link_down_count++; in rge_phy_check()
333 if (rgep->link_down_count > 15) { in rge_phy_check()
334 (void) rge_phy_reset(rgep); in rge_phy_check()
335 rgep->stats.phy_reset++; in rge_phy_check()
336 rgep->link_down_count = 0; in rge_phy_check()
341 rgep->link_down_count = 0; in rge_phy_check()
352 rge_phy_reset(rge_t *rgep) in rge_phy_reset() argument
360 control = rge_mii_get16(rgep, MII_CONTROL); in rge_phy_reset()
361 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); in rge_phy_reset()
364 control = rge_mii_get16(rgep, MII_CONTROL); in rge_phy_reset()
369 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); in rge_phy_reset()
387 rge_phy_update(rge_t *rgep) in rge_phy_update() argument
403 ASSERT(mutex_owned(rgep->genlock)); in rge_phy_update()
410 rgep->param_adv_autoneg, in rge_phy_update()
411 rgep->param_adv_pause, rgep->param_adv_asym_pause, in rge_phy_update()
412 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, in rge_phy_update()
413 rgep->param_adv_100fdx, rgep->param_adv_100hdx, in rge_phy_update()
414 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); in rge_phy_update()
427 switch (rgep->param_loop_mode) { in rge_phy_update()
430 adv_autoneg = rgep->param_adv_autoneg; in rge_phy_update()
431 adv_pause = rgep->param_adv_pause; in rge_phy_update()
432 adv_asym_pause = rgep->param_adv_asym_pause; in rge_phy_update()
433 adv_1000fdx = rgep->param_adv_1000fdx; in rge_phy_update()
434 adv_1000hdx = rgep->param_adv_1000hdx; in rge_phy_update()
435 adv_100fdx = rgep->param_adv_100fdx; in rge_phy_update()
436 adv_100hdx = rgep->param_adv_100hdx; in rge_phy_update()
437 adv_10fdx = rgep->param_adv_10fdx; in rge_phy_update()
438 adv_10hdx = rgep->param_adv_10hdx; in rge_phy_update()
446 rgep->param_link_duplex = LINK_DUPLEX_FULL; in rge_phy_update()
448 switch (rgep->param_loop_mode) { in rge_phy_update()
450 if (rgep->chipid.mac_ver != MAC_VER_8101E) { in rge_phy_update()
451 rgep->param_link_speed = 1000; in rge_phy_update()
454 rgep->param_link_speed = 100; in rge_phy_update()
461 if (rgep->chipid.mac_ver != MAC_VER_8101E) { in rge_phy_update()
462 rgep->param_link_speed = 1000; in rge_phy_update()
465 rgep->param_link_speed = 100; in rge_phy_update()
489 if (rgep->chipid.mac_ver != MAC_VER_8101E) { in rge_phy_update()
529 if (rgep->chipid.is_pcie) in rge_phy_update()
564 rge_phy_init(rgep); in rge_phy_update()
565 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || in rge_phy_update()
566 rgep->chipid.mac_ver == MAC_VER_8168B_C) { in rge_phy_update()
568 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_update()
569 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); in rge_phy_update()
570 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_update()
572 rge_mii_put16(rgep, MII_AN_ADVERT, anar); in rge_phy_update()
573 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); in rge_phy_update()
574 rge_mii_put16(rgep, MII_CONTROL, control); in rge_phy_update()
581 void rge_phy_init(rge_t *rgep);
585 rge_phy_init(rge_t *rgep) in rge_phy_init() argument
587 rgep->phy_mii_addr = 1; in rge_phy_init()
593 switch (rgep->chipid.mac_ver) { in rge_phy_init()
596 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); in rge_phy_init()
597 rge_mii_put16(rgep, PHY_15_REG, 0x1000); in rge_phy_init()
598 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); in rge_phy_init()
599 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); in rge_phy_init()
600 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); in rge_phy_init()
601 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); in rge_phy_init()
602 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); in rge_phy_init()
603 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); in rge_phy_init()
604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); in rge_phy_init()
605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); in rge_phy_init()
606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); in rge_phy_init()
607 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); in rge_phy_init()
608 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); in rge_phy_init()
609 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); in rge_phy_init()
610 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); in rge_phy_init()
611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); in rge_phy_init()
612 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); in rge_phy_init()
613 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); in rge_phy_init()
614 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); in rge_phy_init()
615 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); in rge_phy_init()
616 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); in rge_phy_init()
617 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); in rge_phy_init()
618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); in rge_phy_init()
619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); in rge_phy_init()
620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); in rge_phy_init()
621 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); in rge_phy_init()
622 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); in rge_phy_init()
623 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); in rge_phy_init()
624 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); in rge_phy_init()
625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); in rge_phy_init()
626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); in rge_phy_init()
627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); in rge_phy_init()
628 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); in rge_phy_init()
629 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); in rge_phy_init()
630 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); in rge_phy_init()
631 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); in rge_phy_init()
632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); in rge_phy_init()
633 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); in rge_phy_init()
634 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); in rge_phy_init()
635 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_init()
636 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); in rge_phy_init()
640 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); in rge_phy_init()
641 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); in rge_phy_init()
642 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); in rge_phy_init()
643 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); in rge_phy_init()
644 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); in rge_phy_init()
645 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); in rge_phy_init()
646 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_init()
650 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); in rge_phy_init()
651 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); in rge_phy_init()
652 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); in rge_phy_init()
653 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); in rge_phy_init()
654 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); in rge_phy_init()
655 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); in rge_phy_init()
656 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); in rge_phy_init()
657 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); in rge_phy_init()
658 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); in rge_phy_init()
659 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); in rge_phy_init()
660 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); in rge_phy_init()
661 rge_mii_put16(rgep, PHY_13_REG, 0x0600); in rge_phy_init()
662 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_init()
666 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); in rge_phy_init()
667 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); in rge_phy_init()
668 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); in rge_phy_init()
669 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); in rge_phy_init()
670 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); in rge_phy_init()
671 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); in rge_phy_init()
672 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); in rge_phy_init()
673 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); in rge_phy_init()
674 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); in rge_phy_init()
675 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); in rge_phy_init()
676 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_init()
681 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); in rge_phy_init()
682 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); in rge_phy_init()
683 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); in rge_phy_init()
684 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); in rge_phy_init()
685 rge_mii_put16(rgep, PHY_12_REG, 0x6096); in rge_phy_init()
686 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); in rge_phy_init()
691 void rge_chip_ident(rge_t *rgep);
695 rge_chip_ident(rge_t *rgep) in rge_chip_ident() argument
697 chip_id_t *chip = &rgep->chipid; in rge_chip_ident()
704 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); in rge_chip_ident()
707 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle, in rge_chip_ident()
721 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); in rge_chip_ident()
730 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); in rge_chip_ident()
733 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); in rge_chip_ident()
736 rge_reg_put32(rgep, 0x7c, 0x000700ff); in rge_chip_ident()
738 rge_reg_put32(rgep, 0x7c, 0x0007ff00); in rge_chip_ident()
747 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; in rge_chip_ident()
748 if (rgep->default_mtu > ETHERMTU) { in rge_chip_ident()
749 rge_notice(rgep, "Jumbo packets not supported " in rge_chip_ident()
751 rgep->default_mtu = ETHERMTU; in rge_chip_ident()
754 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) in rge_chip_ident()
755 rgep->head_room = 0; in rge_chip_ident()
757 rgep->head_room = RGE_HEADROOM; in rge_chip_ident()
762 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) in rge_chip_ident()
763 rgep->default_mtu = ETHERMTU; in rge_chip_ident()
764 if (rgep->default_mtu > ETHERMTU) { in rge_chip_ident()
765 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; in rge_chip_ident()
766 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; in rge_chip_ident()
767 rgep->ethmax_size = RGE_JUMBO_SIZE; in rge_chip_ident()
769 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; in rge_chip_ident()
770 rgep->txbuf_size = RGE_BUFF_SIZE_STD; in rge_chip_ident()
771 rgep->ethmax_size = ETHERMAX; in rge_chip_ident()
777 rgep->tick_delta = drv_usectohz(1000*1000/CLK_TICK); in rge_chip_ident()
780 rgep->curr_tick = ddi_get_lbolt() - 2*rgep->tick_delta; in rge_chip_ident()
782 rgep->ifname, chip->mac_ver, chip->phy_ver)); in rge_chip_ident()
794 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp);
798 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) in rge_chip_cfg_init() argument
803 handle = rgep->cfg_handle; in rge_chip_cfg_init()
833 int rge_chip_reset(rge_t *rgep);
837 rge_chip_reset(rge_t *rgep) in rge_chip_reset() argument
845 rge_reg_clr8(rgep, RT_COMMAND_REG, in rge_chip_reset()
851 rgep->int_mask = INT_MASK_NONE; in rge_chip_reset()
852 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); in rge_chip_reset()
857 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); in rge_chip_reset()
862 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); in rge_chip_reset()
869 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); in rge_chip_reset()
871 rgep->rge_chip_state = RGE_CHIP_RESET; in rge_chip_reset()
875 RGE_REPORT((rgep, "rge_chip_reset fail.")); in rge_chip_reset()
879 void rge_chip_init(rge_t *rgep);
883 rge_chip_init(rge_t *rgep) in rge_chip_init() argument
888 chip_id_t *chip = &rgep->chipid; in rge_chip_init()
896 rge_ephy_put16(rgep, 0x01, 0x1bd3); in rge_chip_init()
901 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); in rge_chip_init()
903 rge_reg_put16(rgep, PHY_STATUS_REG, val16); in rge_chip_init()
904 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); in rge_chip_init()
905 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); in rge_chip_init()
906 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); in rge_chip_init()
907 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); in rge_chip_init()
908 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); in rge_chip_init()
909 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); in rge_chip_init()
912 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); in rge_chip_init()
913 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); in rge_chip_init()
919 rgep->param_link_up = LINK_STATE_DOWN; in rge_chip_init()
920 rge_phy_update(rgep); in rge_chip_init()
927 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); in rge_chip_init()
931 rge_reg_put8(rgep, RESV_82_REG, 0x01); in rge_chip_init()
937 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); in rge_chip_init()
943 rge_reg_set8(rgep, RT_COMMAND_REG, in rge_chip_init()
949 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; in rge_chip_init()
950 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); in rge_chip_init()
951 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); in rge_chip_init()
953 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; in rge_chip_init()
954 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); in rge_chip_init()
959 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_chip_init()
964 if (rgep->default_mtu > ETHERMTU) { in rge_chip_init()
965 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); in rge_chip_init()
966 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); in rge_chip_init()
967 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { in rge_chip_init()
968 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); in rge_chip_init()
969 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); in rge_chip_init()
971 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); in rge_chip_init()
972 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); in rge_chip_init()
978 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); in rge_chip_init()
980 if (rgep->promisc) in rge_chip_init()
982 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); in rge_chip_init()
987 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); in rge_chip_init()
989 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); in rge_chip_init()
994 val32 = rgep->tx_desc.cookie.dmac_laddress; in rge_chip_init()
995 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); in rge_chip_init()
996 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; in rge_chip_init()
997 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); in rge_chip_init()
998 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); in rge_chip_init()
999 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); in rge_chip_init()
1000 val32 = rgep->rx_desc.cookie.dmac_laddress; in rge_chip_init()
1001 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); in rge_chip_init()
1002 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; in rge_chip_init()
1003 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); in rge_chip_init()
1008 if (rgep->chipid.mac_ver != MAC_VER_8101E) in rge_chip_init()
1009 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); in rge_chip_init()
1011 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); in rge_chip_init()
1016 hashp = (uint32_t *)rgep->mcast_hash; in rge_chip_init()
1017 if (rgep->promisc) { in rge_chip_init()
1018 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); in rge_chip_init()
1019 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); in rge_chip_init()
1021 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); in rge_chip_init()
1022 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); in rge_chip_init()
1031 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); in rge_chip_init()
1032 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); in rge_chip_init()
1033 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); in rge_chip_init()
1038 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME); in rge_chip_init()
1043 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_chip_init()
1051 void rge_chip_start(rge_t *rgep);
1055 rge_chip_start(rge_t *rgep) in rge_chip_start() argument
1060 bzero(&rgep->stats, sizeof (rge_stats_t)); in rge_chip_start()
1061 DMA_ZERO(rgep->dma_area_stats); in rge_chip_start()
1066 rge_reg_set8(rgep, RT_COMMAND_REG, in rge_chip_start()
1072 rgep->int_mask = RGE_INT_MASK; in rge_chip_start()
1073 if (rgep->chipid.is_pcie) { in rge_chip_start()
1074 rgep->int_mask |= NO_TXDESC_INT; in rge_chip_start()
1076 rgep->rx_fifo_ovf = 0; in rge_chip_start()
1077 rgep->int_mask |= RX_FIFO_OVERFLOW_INT; in rge_chip_start()
1078 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); in rge_chip_start()
1083 rgep->rge_chip_state = RGE_CHIP_RUNNING; in rge_chip_start()
1093 void rge_chip_stop(rge_t *rgep, boolean_t fault);
1097 rge_chip_stop(rge_t *rgep, boolean_t fault) in rge_chip_stop() argument
1102 rgep->int_mask = INT_MASK_NONE; in rge_chip_stop()
1103 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); in rge_chip_stop()
1108 if (!rgep->suspended) { in rge_chip_stop()
1109 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); in rge_chip_stop()
1115 rge_reg_clr8(rgep, RT_COMMAND_REG, in rge_chip_stop()
1119 rgep->rge_chip_state = RGE_CHIP_FAULT; in rge_chip_stop()
1121 rgep->rge_chip_state = RGE_CHIP_STOPPED; in rge_chip_stop()
1127 static void rge_get_mac_addr(rge_t *rgep);
1131 rge_get_mac_addr(rge_t *rgep) in rge_get_mac_addr() argument
1133 uint8_t *macaddr = rgep->netaddr; in rge_get_mac_addr()
1139 val32 = rge_reg_get32(rgep, ID_0_REG); in rge_get_mac_addr()
1151 val32 = rge_reg_get32(rgep, ID_4_REG); in rge_get_mac_addr()
1157 static void rge_set_mac_addr(rge_t *rgep);
1161 rge_set_mac_addr(rge_t *rgep) in rge_set_mac_addr() argument
1163 uint8_t *p = rgep->netaddr; in rge_set_mac_addr()
1169 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_set_mac_addr()
1185 rge_reg_put32(rgep, ID_0_REG, val32); in rge_set_mac_addr()
1197 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; in rge_set_mac_addr()
1198 rge_reg_put32(rgep, ID_4_REG, val32); in rge_set_mac_addr()
1203 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_set_mac_addr()
1206 static void rge_set_multi_addr(rge_t *rgep);
1210 rge_set_multi_addr(rge_t *rgep) in rge_set_multi_addr() argument
1214 hashp = (uint32_t *)rgep->mcast_hash; in rge_set_multi_addr()
1219 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { in rge_set_multi_addr()
1220 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_set_multi_addr()
1222 if (rgep->promisc) { in rge_set_multi_addr()
1223 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); in rge_set_multi_addr()
1224 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); in rge_set_multi_addr()
1226 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); in rge_set_multi_addr()
1227 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); in rge_set_multi_addr()
1233 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { in rge_set_multi_addr()
1234 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); in rge_set_multi_addr()
1238 static void rge_set_promisc(rge_t *rgep);
1242 rge_set_promisc(rge_t *rgep) in rge_set_promisc() argument
1244 if (rgep->promisc) in rge_set_promisc()
1245 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); in rge_set_promisc()
1247 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); in rge_set_promisc()
1255 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo);
1259 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) in rge_chip_sync() argument
1263 rge_get_mac_addr(rgep); in rge_chip_sync()
1267 rge_set_mac_addr(rgep); in rge_chip_sync()
1271 rge_set_multi_addr(rgep); in rge_chip_sync()
1275 rge_set_multi_addr(rgep); in rge_chip_sync()
1276 rge_set_promisc(rgep); in rge_chip_sync()
1293 void rge_tx_trigger(rge_t *rgep);
1297 rge_tx_trigger(rge_t *rgep) in rge_tx_trigger() argument
1299 rge_reg_put8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); in rge_tx_trigger()
1302 void rge_hw_stats_dump(rge_t *rgep);
1306 rge_hw_stats_dump(rge_t *rgep) in rge_hw_stats_dump() argument
1311 if (rgep->rge_mac_state == RGE_MAC_STOPPED) in rge_hw_stats_dump()
1314 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); in rge_hw_stats_dump()
1319 rgep->rge_chip_state = RGE_CHIP_ERROR; in rge_hw_stats_dump()
1322 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); in rge_hw_stats_dump()
1324 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); in rge_hw_stats_dump()
1329 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); in rge_hw_stats_dump()
1339 static void rge_wake_factotum(rge_t *rgep);
1343 rge_wake_factotum(rge_t *rgep) in rge_wake_factotum() argument
1345 if (rgep->factotum_flag == 0) { in rge_wake_factotum()
1346 rgep->factotum_flag = 1; in rge_wake_factotum()
1347 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); in rge_wake_factotum()
1360 rge_t *rgep = (rge_t *)arg1; in rge_intr() local
1373 mutex_enter(rgep->genlock); in rge_intr()
1375 if (rgep->suspended) { in rge_intr()
1376 mutex_exit(rgep->genlock); in rge_intr()
1383 int_status = rge_reg_get16(rgep, INT_STATUS_REG); in rge_intr()
1384 if (!(int_status & rgep->int_mask)) { in rge_intr()
1385 mutex_exit(rgep->genlock); in rge_intr()
1389 rgep->stats.intr++; in rge_intr()
1395 if (rgep->chipid.is_pcie) { in rge_intr()
1396 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); in rge_intr()
1399 rge_reg_put16(rgep, INT_STATUS_REG, int_status); in rge_intr()
1405 if (now - rgep->curr_tick >= rgep->tick_delta && in rge_intr()
1406 (rgep->param_link_speed == RGE_SPEED_1000M || in rge_intr()
1407 rgep->param_link_speed == RGE_SPEED_100M)) { in rge_intr()
1409 tx_pkts = rgep->stats.opackets - rgep->last_opackets; in rge_intr()
1410 rx_pkts = rgep->stats.rpackets - rgep->last_rpackets; in rge_intr()
1412 rgep->last_opackets = rgep->stats.opackets; in rge_intr()
1413 rgep->last_rpackets = rgep->stats.rpackets; in rge_intr()
1416 rgep->int_mask |= TX_OK_INT | RX_OK_INT; in rge_intr()
1417 if (rgep->chipid.is_pcie) { in rge_intr()
1418 rgep->int_mask |= NO_TXDESC_INT; in rge_intr()
1422 if (rgep->param_link_speed == RGE_SPEED_1000M) { in rge_intr()
1433 if (now - rgep->curr_tick < 2*rgep->tick_delta) { in rge_intr()
1437 rgep->int_mask &= ~(TX_OK_INT | NO_TXDESC_INT); in rge_intr()
1444 rgep->int_mask &= ~RX_OK_INT; in rge_intr()
1452 if (rgep->chipid.is_pcie) { in rge_intr()
1462 __func__, itimer, rgep->int_mask)); in rge_intr()
1463 rge_reg_put32(rgep, TIMER_INT_REG, itimer); in rge_intr()
1466 rgep->curr_tick = now; in rge_intr()
1475 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); in rge_intr()
1479 (void) rge_reg_get16(rgep, INT_STATUS_REG); in rge_intr()
1485 rge_chip_cyclic(rgep); in rge_intr()
1490 rgep->rx_fifo_ovf = 1; in rge_intr()
1491 if (rgep->int_mask & RX_FIFO_OVERFLOW_INT) { in rge_intr()
1492 rgep->int_mask &= ~RX_FIFO_OVERFLOW_INT; in rge_intr()
1497 rgep->rx_fifo_ovf = 0; in rge_intr()
1498 if ((rgep->int_mask & RX_FIFO_OVERFLOW_INT) == 0) { in rge_intr()
1499 rgep->int_mask |= RX_FIFO_OVERFLOW_INT; in rge_intr()
1504 mutex_exit(rgep->genlock); in rge_intr()
1510 rge_receive(rgep); in rge_intr()
1516 RGE_REPORT((rgep, "tx error happened, resetting the chip ")); in rge_intr()
1517 mutex_enter(rgep->genlock); in rge_intr()
1518 rgep->rge_chip_state = RGE_CHIP_ERROR; in rge_intr()
1519 mutex_exit(rgep->genlock); in rge_intr()
1520 } else if ((rgep->chipid.is_pcie && (int_status & NO_TXDESC_INT)) || in rge_intr()
1521 ((int_status & TX_OK_INT) && rgep->tx_free < RGE_SEND_SLOTS/8)) { in rge_intr()
1522 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); in rge_intr()
1529 RGE_REPORT((rgep, "sys error happened, resetting the chip ")); in rge_intr()
1530 mutex_enter(rgep->genlock); in rge_intr()
1531 rgep->rge_chip_state = RGE_CHIP_ERROR; in rge_intr()
1532 mutex_exit(rgep->genlock); in rge_intr()
1539 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); in rge_intr()
1551 static boolean_t rge_factotum_link_check(rge_t *rgep);
1555 rge_factotum_link_check(rge_t *rgep) in rge_factotum_link_check() argument
1560 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); in rge_factotum_link_check()
1563 if (rgep->param_link_up != link) { in rge_factotum_link_check()
1567 rgep->param_link_up = link; in rge_factotum_link_check()
1571 rgep->param_link_speed = RGE_SPEED_1000M; in rge_factotum_link_check()
1572 rgep->param_link_duplex = LINK_DUPLEX_FULL; in rge_factotum_link_check()
1574 rgep->param_link_speed = in rge_factotum_link_check()
1577 rgep->param_link_duplex = in rge_factotum_link_check()
1590 static boolean_t rge_factotum_stall_check(rge_t *rgep);
1594 rge_factotum_stall_check(rge_t *rgep) in rge_factotum_stall_check() argument
1598 ASSERT(mutex_owned(rgep->genlock)); in rge_factotum_stall_check()
1603 rgep->rx_fifo_ovf <<= 1; in rge_factotum_stall_check()
1604 if (rgep->rx_fifo_ovf > rge_rx_watchdog_count) { in rge_factotum_stall_check()
1605 RGE_REPORT((rgep, "rx_hang detected")); in rge_factotum_stall_check()
1623 if (rgep->resched_needed) in rge_factotum_stall_check()
1624 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); in rge_factotum_stall_check()
1625 dogval = rge_atomic_shl32(&rgep->watchdog, 1); in rge_factotum_stall_check()
1629 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); in rge_factotum_stall_check()
1647 rge_t *rgep; in rge_chip_factotum() local
1652 rgep = (rge_t *)arg1; in rge_chip_factotum()
1655 if (rgep->factotum_flag == 0) in rge_chip_factotum()
1658 rgep->factotum_flag = 0; in rge_chip_factotum()
1663 mutex_enter(rgep->genlock); in rge_chip_factotum()
1664 switch (rgep->rge_chip_state) { in rge_chip_factotum()
1669 linkchg = rge_factotum_link_check(rgep); in rge_chip_factotum()
1670 error = rge_factotum_stall_check(rgep); in rge_chip_factotum()
1682 RGE_REPORT((rgep, "automatic recovery activated")); in rge_chip_factotum()
1683 rge_restart(rgep); in rge_chip_factotum()
1693 rge_chip_stop(rgep, B_TRUE); in rge_chip_factotum()
1694 mutex_exit(rgep->genlock); in rge_chip_factotum()
1701 mac_link_update(rgep->mh, rgep->param_link_up); in rge_chip_factotum()
1719 rge_t *rgep; in rge_chip_cyclic() local
1721 rgep = arg; in rge_chip_cyclic()
1723 switch (rgep->rge_chip_state) { in rge_chip_cyclic()
1728 rge_phy_check(rgep); in rge_chip_cyclic()
1729 if (rgep->tx_free < RGE_SEND_SLOTS) in rge_chip_cyclic()
1730 rge_send_recycle(rgep); in rge_chip_cyclic()
1738 rge_wake_factotum(rgep); in rge_chip_cyclic()
1751 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1755 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_peek_cfg() argument
1761 (void *)rgep, (void *)ppd)); in rge_chip_peek_cfg()
1767 regval = pci_config_get8(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1771 regval = pci_config_get16(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1775 regval = pci_config_get32(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1779 regval = pci_config_get64(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1786 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
1790 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_poke_cfg() argument
1796 (void *)rgep, (void *)ppd)); in rge_chip_poke_cfg()
1803 pci_config_put8(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1807 pci_config_put16(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1811 pci_config_put32(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1815 pci_config_put64(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1820 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1824 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_peek_reg() argument
1830 (void *)rgep, (void *)ppd)); in rge_chip_peek_reg()
1832 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); in rge_chip_peek_reg()
1836 regval = ddi_get8(rgep->io_handle, regaddr); in rge_chip_peek_reg()
1840 regval = ddi_get16(rgep->io_handle, regaddr); in rge_chip_peek_reg()
1844 regval = ddi_get32(rgep->io_handle, regaddr); in rge_chip_peek_reg()
1848 regval = ddi_get64(rgep->io_handle, regaddr); in rge_chip_peek_reg()
1855 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd);
1859 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_poke_reg() argument
1865 (void *)rgep, (void *)ppd)); in rge_chip_poke_reg()
1867 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); in rge_chip_poke_reg()
1872 ddi_put8(rgep->io_handle, regaddr, regval); in rge_chip_poke_reg()
1876 ddi_put16(rgep->io_handle, regaddr, regval); in rge_chip_poke_reg()
1880 ddi_put32(rgep->io_handle, regaddr, regval); in rge_chip_poke_reg()
1884 ddi_put64(rgep->io_handle, regaddr, regval); in rge_chip_poke_reg()
1889 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1893 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_peek_mii() argument
1896 (void *)rgep, (void *)ppd)); in rge_chip_peek_mii()
1898 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); in rge_chip_peek_mii()
1901 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd);
1905 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_poke_mii() argument
1908 (void *)rgep, (void *)ppd)); in rge_chip_poke_mii()
1910 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); in rge_chip_poke_mii()
1913 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1917 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_peek_mem() argument
1923 (void *)rgep, (void *)ppd)); in rge_chip_peek_mem()
1946 (void *)rgep, (void *)ppd, regval, vaddr)); in rge_chip_peek_mem()
1951 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd);
1955 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) in rge_chip_poke_mem() argument
1961 (void *)rgep, (void *)ppd)); in rge_chip_poke_mem()
1967 (void *)rgep, (void *)ppd, regval, vaddr)); in rge_chip_poke_mem()
1988 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
1993 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) in rge_pp_ioctl() argument
1995 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); in rge_pp_ioctl()
2006 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); in rge_pp_ioctl()
2074 mem_va = (uintptr_t)rgep; in rge_pp_ioctl()
2075 maxoff = sizeof (*rgep); in rge_pp_ioctl()
2089 areap = &rgep->dma_area_txdesc; in rge_pp_ioctl()
2092 areap = &rgep->dma_area_rxdesc; in rge_pp_ioctl()
2095 areap = &rgep->dma_area_stats; in rge_pp_ioctl()
2132 (*ppfn)(rgep, ppd); in rge_pp_ioctl()
2136 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2141 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) in rge_diag_ioctl() argument
2143 ASSERT(mutex_owned(rgep->genlock)); in rge_diag_ioctl()
2148 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); in rge_diag_ioctl()
2159 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); in rge_diag_ioctl()
2169 rge_restart(rgep); in rge_diag_ioctl()
2178 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
2183 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) in rge_mii_ioctl() argument
2205 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); in rge_mii_ioctl()
2209 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); in rge_mii_ioctl()
2213 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); in rge_mii_ioctl()
2220 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
2225 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) in rge_chip_ioctl() argument
2230 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); in rge_chip_ioctl()
2232 ASSERT(mutex_owned(rgep->genlock)); in rge_chip_ioctl()
2238 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); in rge_chip_ioctl()
2248 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); in rge_chip_ioctl()
2255 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); in rge_chip_ioctl()